registers/display/hdmi.xml

1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
7 <!--
11  -->
43 		<bitfield name="ENABLE" pos="0" type="boolean"/>
44 		<bitfield name="HDMI" pos="1" type="boolean"/>
45 		<bitfield name="ENCRYPTED" pos="2" type="boolean"/>
48 		<bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
51 		<!--
59 		 -->
60 		<bitfield name="CONT" pos="0" type="boolean"/>
61 		<bitfield name="SEND" pos="1" type="boolean"/>
63 		<bitfield name="SOURCE" pos="8" type="boolean"/>
65 		<bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
68 		<!--
79 		 -->
80 		<bitfield name="GC_ENABLE" pos="4" type="boolean"/>
81 		<bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
82 		<bitfield name="ISRC_SEND" pos="8" type="boolean"/>
83 		<bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
84 		<bitfield name="ACP_SEND" pos="12" type="boolean"/>
85 		<bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
88 		<!--
96 		 -->
97 		<bitfield name="AVI_SEND" pos="0" type="boolean"/>
98 		<bitfield name="AVI_CONT" pos="1" type="boolean"/>           <!-- every frame -->
99 		<bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
100 		<bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/>    <!-- every frame -->
101 		<bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
102 		<bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
111 		<!--
131 		 -->
132 		<bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
133 		<bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
134 		<bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
135 		<bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
136 		<bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
141 		<bitfield name="MUTE" pos="0" type="boolean"/>
144 		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
145 		<bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
148 	<!--
151 	-->
160 	<!--
161 		TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
162 	 -->
168 			<!-- not sure the actual # of bits.. -->
175 		<bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
178 		<bitfield name="CA" low="0" high="7"/>        <!-- Channel Allocation -->
179 		<bitfield name="LSV" low="11" high="14"/>     <!-- Level Shift -->
180 		<bitfield name="DM_INH" pos="15" type="boolean"/>  <!-- down-mix inhibit flag -->
183 		<bitfield name="ENABLE" pos="0" type="boolean"/>
184 		<bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
187 		<bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
190 		<bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
191 		<bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
192 		<bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
193 		<bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
194 		<bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
195 		<bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
196 		<bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
197 		<bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
198 		<bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
199 		<bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
200 		<bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
201 		<bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
202 		<bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
205 		<bitfield name="AN_0_READY" pos="8" type="boolean"/>
206 		<bitfield name="AN_1_READY" pos="9" type="boolean"/>
207 		<bitfield name="RI_MATCHES" pos="12" type="boolean"/>
208 		<bitfield name="V_MATCHES" pos="20" type="boolean"/>
212 		<bitfield name="DISABLE" pos="0" type="boolean"/>
215 		<bitfield name="FAILED_ACK" pos="0" type="boolean"/>
218 		<bitfield name="XFER_REQ" pos="4" type="boolean"/>
219 		<bitfield name="XFER_DONE" pos="10" type="boolean"/>
220 		<bitfield name="ABORTED" pos="12" type="boolean"/>
221 		<bitfield name="TIMEOUT" pos="13" type="boolean"/>
222 		<bitfield name="NACK0" pos="14" type="boolean"/>
223 		<bitfield name="NACK1" pos="15" type="boolean"/>
224 		<bitfield name="FAILED" pos="16" type="boolean"/>
231 		<bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
258 		<bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
264 		<!--
281 		 -->
282 		<bitfield name="GO" pos="0" type="boolean"/>
283 		<bitfield name="SOFT_RESET" pos="1" type="boolean"/>
284 		<bitfield name="SEND_RESET" pos="2" type="boolean"/>
285 		<bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
289 		<bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
292 		<!--
299 		 -->
300 		<bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
301 		<bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
302 		<bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
305 		<bitfield name="NACK0" pos="12" type="boolean"/>
306 		<bitfield name="NACK1" pos="13" type="boolean"/>
307 		<bitfield name="NACK2" pos="14" type="boolean"/>
308 		<bitfield name="NACK3" pos="15" type="boolean"/>
311 		<bitfield name="DONE" pos="3" type="boolean"/>
314 		<!--
327 		 -->
332 		<!--
336 		 -->
339 	<!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
342 			<!--
359 				[0] RW0 Read/write indicator for first transaction - set to 0 for
360 					write, 1 for read. This bit only controls HDMI_DDC behaviour -
365 			 -->
366 			<bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
367 			<bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
368 			<bitfield name="START" pos="12" type="boolean"/>
369 			<bitfield name="STOP" pos="13" type="boolean"/>
374 		<!--
383 				For writes, address auto-increments on write to HDMI_DDC_DATA.
387 		 -->
388 		<bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
391 		<bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
396 		<bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
397 		<bitfield name="COMP_DONE" pos="4" type="boolean"/>
400 		<bitfield name="DONE" pos="0" type="boolean"/>
404 		<bitfield name="INT" pos="0" type="boolean"/>  <!-- an irq has occurred -->
405 		<bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
408 		<!-- (this useful comment was removed in df6b645.. git archaeology is fun)
429 		 -->
430 		<bitfield name="INT_ACK" pos="0" type="boolean"/>
431 		<bitfield name="INT_CONNECT" pos="1" type="boolean"/>
432 		<bitfield name="INT_EN" pos="2" type="boolean"/>
433 		<bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
434 		<bitfield name="RX_INT_EN" pos="5" type="boolean"/>
435 		<bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
439 		<bitfield name="ENABLE" pos="28" type="boolean"/>
442 		<!--
448 				DDC strobe. This register counts on HDCP application clock
451 			 * 27 micro-seconds */
453 		 -->
454 		<bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
462 		<bitfield name="ENABLE" pos="0" type="boolean"/>
463 		<bitfield name="SEND_TRIGGER" pos="1" type="boolean"/>
465 		<bitfield name="LINE_OE" pos="9" type="boolean"/>
468 		<bitfield name="BROADCAST" pos="0" type="boolean"/>
472 		<bitfield name="ENABLE" pos="0" type="boolean"/>
476 		<bitfield name="BUSY" pos="0" type="boolean"/>
477 		<bitfield name="TX_FRAME_DONE" pos="3" type="boolean"/>
481 		<bitfield name="TX_DONE" pos="0" type="boolean"/>
482 		<bitfield name="TX_DONE_MASK" pos="1" type="boolean"/>
483 		<bitfield name="TX_ERROR" pos="2" type="boolean"/>
484 		<bitfield name="TX_ERROR_MASK" pos="3" type="boolean"/>
485 		<bitfield name="MONITOR" pos="4" type="boolean"/>
486 		<bitfield name="MONITOR_MASK" pos="5" type="boolean"/>
487 		<bitfield name="RX_DONE" pos="6" type="boolean"/>
488 		<bitfield name="RX_DONE_MASK" pos="7" type="boolean"/>
492 		<bitfield name="ENABLE" pos="0" type="boolean"/>
497 		<bitfield name="ENABLE" pos="16" type="boolean"/>
514 		<!-- interlaced, frame 2 -->
523 		<!-- interlaced, frame 2 -->
527 		<bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
528 		<bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
529 		<bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
530 		<bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
533 		<!--
539 		 -->
540 		<bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/>  <!-- write to ack irq -->
541 		<bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
542 		<bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/>   <!-- write to ack irq -->
543 		<bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/>  <!-- r/w, enables irq -->
546 		<!--
550 		 -->
551 		<bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
552 		<bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
553 		<bitfield name="SW_RESET" pos="2" type="boolean"/>
554 		<bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
576 		<bitfield name="PD_DESER" pos="0" type="boolean"/>
577 		<bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
578 		<bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
579 		<bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
580 		<bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
581 		<bitfield name="PD_PLL" pos="5" type="boolean"/>
582 		<bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
583 		<bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
586 		<bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
597 		<bitfield name="RETIMING_EN" pos="0" type="boolean"/>
598 		<bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
599 		<bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
604 	<!--
607 	 -->
621 		<bitfield name="SW_RESET" pos="5" type="boolean"/>
622 		<bitfield name="PWRDN_B" pos="7" type="boolean"/>
640 		<bitfield name="PD_PLL" pos="1" type="boolean"/>
641 		<bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
675 		<bitfield name="PLL_LOCK" pos="0" type="boolean"/>
681 	<!--
683 	 -->
715 		<bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
716 		<bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
717 		<bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
718 		<bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
738 		<bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>