registers/display/hdmi.xml

1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
7 <!--
11  -->
51 		<!--
59 		 -->
68 		<!--
79 		 -->
88 		<!--
96 		 -->
98 		<bitfield name="AVI_CONT" pos="1" type="boolean"/>           <!-- every frame -->
100 		<bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/>    <!-- every frame -->
111 		<!--
131 		 -->
134 		<bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
145 		<bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
148 	<!--
151 	-->
160 	<!--
161 		TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
162 	 -->
168 			<!-- not sure the actual # of bits.. -->
175 		<bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
178 		<bitfield name="CA" low="0" high="7"/>        <!-- Channel Allocation -->
179 		<bitfield name="LSV" low="11" high="14"/>     <!-- Level Shift -->
180 		<bitfield name="DM_INH" pos="15" type="boolean"/>  <!-- down-mix inhibit flag -->
264 		<!--
281 		 -->
292 		<!--
299 		 -->
314 		<!--
319 		   [1:0]   THRESHOLD Select threshold to use to determine whether value
327 		 -->
328 		<bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
332 		<!--
336 		 -->
339 	<!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
342 			<!--
359 				[0] RW0 Read/write indicator for first transaction - set to 0 for
360 					write, 1 for read. This bit only controls HDMI_DDC behaviour -
365 			 -->
374 		<!--
383 				For writes, address auto-increments on write to HDMI_DDC_DATA.
387 		 -->
404 		<bitfield name="INT" pos="0" type="boolean"/>  <!-- an irq has occurred -->
408 		<!-- (this useful comment was removed in df6b645.. git archaeology is fun)
429 		 -->
442 		<!--
451 			 * 27 micro-seconds */
453 		 -->
514 		<!-- interlaced, frame 2 -->
523 		<!-- interlaced, frame 2 -->
533 		<!--
539 		 -->
540 		<bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/>  <!-- write to ack irq -->
541 		<bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
542 		<bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/>   <!-- write to ack irq -->
543 		<bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/>  <!-- r/w, enables irq -->
546 		<!--
550 		 -->
604 	<!--
607 	 -->
681 	<!--
683 	 -->
909 	<reg32 offset="0x0014C" name="SAR"/>