Lines Matching +full:0 +full:x80000100
15 <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
25 <value name="DDC_WRITE" value="0"/>
29 <value name="ACR_NONE" value="0"/>
36 <value name="CEC_TX_OK" value="0"/>
42 <reg32 offset="0x00000" name="CTRL">
43 <bitfield name="ENABLE" pos="0" type="boolean"/>
47 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
48 <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
50 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
54 acr_pck_ctrl_reg |= 0x80000100;
58 acr_pck_ctrl_reg |= 0x00000003;
60 <bitfield name="CONT" pos="0" type="boolean"/>
67 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
71 /* HDMI_VBI_PKT_CTRL[0x0028] */
72 hdmi_msm_rmw32or(0x0028, 3 << 4);
73 /* HDMI_VBI_PKT_CTRL[0x0028] */
75 hdmi_msm_rmw32or(0x0028, 3 << 8);
76 /* HDMI_VBI_PKT_CTRL[0x0028] */
78 hdmi_msm_rmw32or(0x0028, 3 << 12);
87 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
93 audio_info_ctrl_reg |= 0x000000F0;
94 /* 0x3 for AVI InfFrame enable (every frame) */
95 HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
97 <bitfield name="AVI_SEND" pos="0" type="boolean"/>
104 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
105 <bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
110 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
112 0x0034 GEN_PKT_CTRL
113 GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
115 GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
118 GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
120 GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
129 Enable HDMI TX engine to transmit Generic packet 0
130 HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
132 <bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
140 <reg32 offset="0x00040" name="GC">
141 <bitfield name="MUTE" pos="0" type="boolean"/>
143 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
144 <bitfield name="OVERRIDE" pos="0" type="boolean"/>
152 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
154 <reg32 offset="0x00084" name="GENERIC0_HDR"/>
155 <reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
157 <reg32 offset="0x000a4" name="GENERIC1_HDR"/>
158 <reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
163 <array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
164 <reg32 offset="0" name="0">
169 <bitfield name="N" low="0" high="31" type="uint"/>
173 <reg32 offset="0x000e4" name="AUDIO_INFO0">
174 <bitfield name="CHECKSUM" low="0" high="7"/>
177 <reg32 offset="0x000e8" name="AUDIO_INFO1">
178 <bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
182 <reg32 offset="0x00110" name="HDCP_CTRL">
183 <bitfield name="ENABLE" pos="0" type="boolean"/>
186 <reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
189 <reg32 offset="0x00118" name="HDCP_INT_CTRL">
190 <bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
204 <reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
211 <reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
212 <bitfield name="DISABLE" pos="0" type="boolean"/>
214 <reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
215 <bitfield name="FAILED_ACK" pos="0" type="boolean"/>
217 <reg32 offset="0x00128" name="HDCP_DDC_STATUS">
227 <reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
228 <reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
230 <reg32 offset="0x00130" name="HDCP_RESET">
231 <bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
234 <reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
235 <reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
236 <reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
237 <reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
238 <reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
239 <reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
240 <reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
241 <reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
242 <reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
243 <reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
244 <reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
245 <reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
246 <reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
247 <reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
249 <reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
250 <reg32 offset="0x00170" name="VENSPEC_INFO1"/>
251 <reg32 offset="0x00174" name="VENSPEC_INFO2"/>
252 <reg32 offset="0x00178" name="VENSPEC_INFO3"/>
253 <reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
254 <reg32 offset="0x00180" name="VENSPEC_INFO5"/>
255 <reg32 offset="0x00184" name="VENSPEC_INFO6"/>
257 <reg32 offset="0x001d0" name="AUDIO_CFG">
258 <bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
262 <reg32 offset="0x00208" name="USEC_REFTIMER"/>
263 <reg32 offset="0x0020c" name="DDC_CTRL">
265 0x020C HDMI_DDC_CTRL
268 * 0x0: transaction0 only
269 * 0x1: transaction0, transaction1
270 * 0x2: transaction0, transaction1, transaction2
271 * 0x3: transaction0, transaction1, transaction2, transaction3
280 [0] GO WRITE ONLY. Write 1 to start DDC transfer.
282 <bitfield name="GO" pos="0" type="boolean"/>
288 <reg32 offset="0x00210" name="DDC_ARBITRATION">
291 <reg32 offset="0x00214" name="DDC_INT_CTRL">
293 HDMI_DDC_INT_CTRL[0x0214]
298 [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
300 <bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
304 <reg32 offset="0x00218" name="DDC_SW_STATUS">
310 <reg32 offset="0x0021c" name="DDC_HW_STATUS">
313 <reg32 offset="0x00220" name="DDC_SPEED">
315 0x0220 HDMI_DDC_SPEED
319 [1:0] THRESHOLD Select threshold to use to determine whether value
320 sampled on SDA is a 1 or 0. Specified in terms of the ratio
323 * 0x0: >0
324 * 0x1: 1/4 of total samples
325 * 0x2: 1/2 of total samples
326 * 0x3: 3/4 of total samples */
328 <bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
331 <reg32 offset="0x00224" name="DDC_SETUP">
333 * 0x0224 HDMI_DDC_SETUP
340 <array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
341 <reg32 offset="0" name="REG">
343 0x0228 HDMI_DDC_TRANS0
348 * 0: NO STOP
352 * 0: NO START
357 * 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
359 [0] RW0 Read/write indicator for first transaction - set to 0 for
363 * 0: WRITE
366 <bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
373 <reg32 offset="0x00238" name="DDC_DATA">
375 0x0238 HDMI_DDC_DATA
382 [0] DATA_RW Select whether buffer access will be a read or write.
385 * 0: Write
388 <bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
394 <reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
395 <reg32 offset="0x00240" name="HDCP_SHA_STATUS">
396 <bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
399 <reg32 offset="0x00244" name="HDCP_SHA_DATA">
400 <bitfield name="DONE" pos="0" type="boolean"/>
403 <reg32 offset="0x00250" name="HPD_INT_STATUS">
404 <bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
407 <reg32 offset="0x00254" name="HPD_INT_CTRL">
409 HPD_INT_CTRL[0x0254]
417 0: Disable
423 0: Disable
426 0: generate interrupt on disconnect
428 0 INT_ACK WRITE ONLY. Panel interrupt ack
430 <bitfield name="INT_ACK" pos="0" type="boolean"/>
437 <reg32 offset="0x00258" name="HPD_CTRL">
438 <bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
441 <reg32 offset="0x0027c" name="DDC_REF">
443 0x027C HDMI_DDC_REF
445 * 0: Disable
447 [15:0] REFTIMER Value to set the register in order to generate
452 HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
455 <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
458 <reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
459 <reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
461 <reg32 offset="0x0028c" name="CEC_CTRL">
462 <bitfield name="ENABLE" pos="0" type="boolean"/>
467 <reg32 offset="0x00290" name="CEC_WR_DATA">
468 <bitfield name="BROADCAST" pos="0" type="boolean"/>
471 <reg32 offset="0x00294" name="CEC_RETRANSMIT">
472 <bitfield name="ENABLE" pos="0" type="boolean"/>
475 <reg32 offset="0x00298" name="CEC_STATUS">
476 <bitfield name="BUSY" pos="0" type="boolean"/>
480 <reg32 offset="0x0029c" name="CEC_INT">
481 <bitfield name="TX_DONE" pos="0" type="boolean"/>
490 <reg32 offset="0x002a0" name="CEC_ADDR"/>
491 <reg32 offset="0x002a4" name="CEC_TIME">
492 <bitfield name="ENABLE" pos="0" type="boolean"/>
495 <reg32 offset="0x002a8" name="CEC_REFTIMER">
496 <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
499 <reg32 offset="0x002ac" name="CEC_RD_DATA">
500 <bitfield name="DATA" low="0" high="7" type="uint"/>
503 <reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
505 <reg32 offset="0x002b4" name="ACTIVE_HSYNC">
506 <bitfield name="START" low="0" high="12" type="uint"/>
509 <reg32 offset="0x002b8" name="ACTIVE_VSYNC">
510 <bitfield name="START" low="0" high="12" type="uint"/>
513 <reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
515 <bitfield name="START" low="0" high="12" type="uint"/>
518 <reg32 offset="0x002c0" name="TOTAL">
519 <bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
522 <reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
524 <bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
526 <reg32 offset="0x002c8" name="FRAME_CTRL">
532 <reg32 offset="0x002cc" name="AUD_INT">
534 HDMI_AUD_INT[0x02CC]
538 [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
540 <bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
545 <reg32 offset="0x002d4" name="PHY_CTRL">
551 <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
556 <reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
557 <reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
558 <reg32 offset="0x002e4" name="VERSION"/>
559 <reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
560 <reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
561 <reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
562 <reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
563 <reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
568 <reg32 offset="0x00000" name="PHY_REG0">
571 <reg32 offset="0x00004" name="PHY_REG1">
573 <bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
575 <reg32 offset="0x00008" name="PHY_REG2">
576 <bitfield name="PD_DESER" pos="0" type="boolean"/>
585 <reg32 offset="0x0000c" name="PHY_REG3">
586 <bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
588 <reg32 offset="0x00010" name="PHY_REG4"/>
589 <reg32 offset="0x00014" name="PHY_REG5"/>
590 <reg32 offset="0x00018" name="PHY_REG6"/>
591 <reg32 offset="0x0001c" name="PHY_REG7"/>
592 <reg32 offset="0x00020" name="PHY_REG8"/>
593 <reg32 offset="0x00024" name="PHY_REG9"/>
594 <reg32 offset="0x00028" name="PHY_REG10"/>
595 <reg32 offset="0x0002c" name="PHY_REG11"/>
596 <reg32 offset="0x00030" name="PHY_REG12">
597 <bitfield name="RETIMING_EN" pos="0" type="boolean"/>
608 <reg32 offset="0x00000" name="PHY_REG0"/>
609 <reg32 offset="0x00004" name="PHY_REG1"/>
610 <reg32 offset="0x00008" name="PHY_REG2"/>
611 <reg32 offset="0x0000c" name="PHY_REG3"/>
612 <reg32 offset="0x00010" name="PHY_REG4"/>
613 <reg32 offset="0x00014" name="PHY_REG5"/>
614 <reg32 offset="0x00018" name="PHY_REG6"/>
615 <reg32 offset="0x0001c" name="PHY_REG7"/>
616 <reg32 offset="0x00020" name="PHY_REG8"/>
617 <reg32 offset="0x00024" name="PHY_REG9"/>
618 <reg32 offset="0x00028" name="PHY_REG10"/>
619 <reg32 offset="0x0002c" name="PHY_REG11"/>
620 <reg32 offset="0x00030" name="PHY_REG12">
624 <reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
625 <reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
626 <reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
627 <reg32 offset="0x00040" name="PHY_REG13"/>
628 <reg32 offset="0x00044" name="PHY_REG14"/>
629 <reg32 offset="0x00048" name="PHY_REG15"/>
633 <reg32 offset="0x00000" name="REFCLK_CFG"/>
634 <reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
635 <reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
636 <reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
637 <reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
638 <reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
639 <reg32 offset="0x00018" name="PWRDN_B">
643 <reg32 offset="0x0001c" name="SDM_CFG0"/>
644 <reg32 offset="0x00020" name="SDM_CFG1"/>
645 <reg32 offset="0x00024" name="SDM_CFG2"/>
646 <reg32 offset="0x00028" name="SDM_CFG3"/>
647 <reg32 offset="0x0002c" name="SDM_CFG4"/>
648 <reg32 offset="0x00030" name="SSC_CFG0"/>
649 <reg32 offset="0x00034" name="SSC_CFG1"/>
650 <reg32 offset="0x00038" name="SSC_CFG2"/>
651 <reg32 offset="0x0003c" name="SSC_CFG3"/>
652 <reg32 offset="0x00040" name="LOCKDET_CFG0"/>
653 <reg32 offset="0x00044" name="LOCKDET_CFG1"/>
654 <reg32 offset="0x00048" name="LOCKDET_CFG2"/>
655 <reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
656 <reg32 offset="0x00050" name="VCOCAL_CFG1"/>
657 <reg32 offset="0x00054" name="VCOCAL_CFG2"/>
658 <reg32 offset="0x00058" name="VCOCAL_CFG3"/>
659 <reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
660 <reg32 offset="0x00060" name="VCOCAL_CFG5"/>
661 <reg32 offset="0x00064" name="VCOCAL_CFG6"/>
662 <reg32 offset="0x00068" name="VCOCAL_CFG7"/>
663 <reg32 offset="0x0006c" name="DEBUG_SEL"/>
664 <reg32 offset="0x00070" name="MISC0"/>
665 <reg32 offset="0x00074" name="MISC1"/>
666 <reg32 offset="0x00078" name="MISC2"/>
667 <reg32 offset="0x0007c" name="MISC3"/>
668 <reg32 offset="0x00080" name="MISC4"/>
669 <reg32 offset="0x00084" name="MISC5"/>
670 <reg32 offset="0x00088" name="MISC6"/>
671 <reg32 offset="0x0008c" name="DEBUG_BUS0"/>
672 <reg32 offset="0x00090" name="DEBUG_BUS1"/>
673 <reg32 offset="0x00094" name="DEBUG_BUS2"/>
674 <reg32 offset="0x00098" name="STATUS0">
675 <bitfield name="PLL_LOCK" pos="0" type="boolean"/>
677 <reg32 offset="0x0009c" name="STATUS1"/>
684 <reg32 offset="0x00000" name="ANA_CFG0"/>
685 <reg32 offset="0x00004" name="ANA_CFG1"/>
686 <reg32 offset="0x00008" name="ANA_CFG2"/>
687 <reg32 offset="0x0000c" name="ANA_CFG3"/>
688 <reg32 offset="0x00010" name="PD_CTRL0"/>
689 <reg32 offset="0x00014" name="PD_CTRL1"/>
690 <reg32 offset="0x00018" name="GLB_CFG"/>
691 <reg32 offset="0x0001c" name="DCC_CFG0"/>
692 <reg32 offset="0x00020" name="DCC_CFG1"/>
693 <reg32 offset="0x00024" name="TXCAL_CFG0"/>
694 <reg32 offset="0x00028" name="TXCAL_CFG1"/>
695 <reg32 offset="0x0002c" name="TXCAL_CFG2"/>
696 <reg32 offset="0x00030" name="TXCAL_CFG3"/>
697 <reg32 offset="0x00034" name="BIST_CFG0"/>
698 <reg32 offset="0x0003c" name="BIST_PATN0"/>
699 <reg32 offset="0x00040" name="BIST_PATN1"/>
700 <reg32 offset="0x00044" name="BIST_PATN2"/>
701 <reg32 offset="0x00048" name="BIST_PATN3"/>
702 <reg32 offset="0x0005c" name="STATUS"/>
706 <reg32 offset="0x00000" name="REFCLK_CFG"/>
707 <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
708 <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
709 <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
710 <reg32 offset="0x00010" name="VREG_CFG"/>
711 <reg32 offset="0x00014" name="PWRGEN_CFG"/>
712 <reg32 offset="0x00018" name="DMUX_CFG"/>
713 <reg32 offset="0x0001C" name="AMUX_CFG"/>
714 <reg32 offset="0x00020" name="GLB_CFG">
715 <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
720 <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
721 <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
722 <reg32 offset="0x0002C" name="LPFR_CFG"/>
723 <reg32 offset="0x00030" name="LPFC1_CFG"/>
724 <reg32 offset="0x00034" name="LPFC2_CFG"/>
725 <reg32 offset="0x00038" name="SDM_CFG0"/>
726 <reg32 offset="0x0003C" name="SDM_CFG1"/>
727 <reg32 offset="0x00040" name="SDM_CFG2"/>
728 <reg32 offset="0x00044" name="SDM_CFG3"/>
729 <reg32 offset="0x00048" name="SDM_CFG4"/>
730 <reg32 offset="0x0004C" name="SSC_CFG0"/>
731 <reg32 offset="0x00050" name="SSC_CFG1"/>
732 <reg32 offset="0x00054" name="SSC_CFG2"/>
733 <reg32 offset="0x00058" name="SSC_CFG3"/>
734 <reg32 offset="0x0005C" name="LKDET_CFG0"/>
735 <reg32 offset="0x00060" name="LKDET_CFG1"/>
736 <reg32 offset="0x00064" name="LKDET_CFG2"/>
737 <reg32 offset="0x00068" name="TEST_CFG">
738 <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
740 <reg32 offset="0x0006C" name="CAL_CFG0"/>
741 <reg32 offset="0x00070" name="CAL_CFG1"/>
742 <reg32 offset="0x00074" name="CAL_CFG2"/>
743 <reg32 offset="0x00078" name="CAL_CFG3"/>
744 <reg32 offset="0x0007C" name="CAL_CFG4"/>
745 <reg32 offset="0x00080" name="CAL_CFG5"/>
746 <reg32 offset="0x00084" name="CAL_CFG6"/>
747 <reg32 offset="0x00088" name="CAL_CFG7"/>
748 <reg32 offset="0x0008C" name="CAL_CFG8"/>
749 <reg32 offset="0x00090" name="CAL_CFG9"/>
750 <reg32 offset="0x00094" name="CAL_CFG10"/>
751 <reg32 offset="0x00098" name="CAL_CFG11"/>
752 <reg32 offset="0x0009C" name="EFUSE_CFG"/>
753 <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
754 <reg32 offset="0x000C0" name="STATUS"/>
758 <reg32 offset="0x00000" name="CFG"/>
759 <reg32 offset="0x00004" name="PD_CTL"/>
760 <reg32 offset="0x00008" name="MODE"/>
761 <reg32 offset="0x0000C" name="MISR_CLEAR"/>
762 <reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
763 <reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
764 <reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
765 <reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
766 <reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
767 <reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
768 <reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
769 <reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
770 <reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
771 <reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
772 <reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
773 <reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
774 <reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
775 <reg32 offset="0x00044" name="TXCAL_CFG0"/>
776 <reg32 offset="0x00048" name="TXCAL_CFG1"/>
777 <reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
778 <reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
779 <reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
780 <reg32 offset="0x00058" name="CLOCK"/>
781 <reg32 offset="0x0005C" name="MISC1"/>
782 <reg32 offset="0x00060" name="MISC2"/>
783 <reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
784 <reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
785 <reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
786 <reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
787 <reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
788 <reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
789 <reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
790 <reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
791 <reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
792 <reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
793 <reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
794 <reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
795 <reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
796 <reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
797 <reg32 offset="0x0009C" name="STATUS"/>
798 <reg32 offset="0x000A0" name="MISC3_STATUS"/>
799 <reg32 offset="0x000A4" name="MISC4_STATUS"/>
800 <reg32 offset="0x000A8" name="DEBUG_BUS0"/>
801 <reg32 offset="0x000AC" name="DEBUG_BUS1"/>
802 <reg32 offset="0x000B0" name="DEBUG_BUS2"/>
803 <reg32 offset="0x000B4" name="DEBUG_BUS3"/>
804 <reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
805 <reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
806 <reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
807 <reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
811 <reg32 offset="0x00000" name="ATB_SEL1"/>
812 <reg32 offset="0x00004" name="ATB_SEL2"/>
813 <reg32 offset="0x00008" name="FREQ_UPDATE"/>
814 <reg32 offset="0x0000C" name="BG_TIMER"/>
815 <reg32 offset="0x00010" name="SSC_EN_CENTER"/>
816 <reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
817 <reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
818 <reg32 offset="0x0001C" name="SSC_PER1"/>
819 <reg32 offset="0x00020" name="SSC_PER2"/>
820 <reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
821 <reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
822 <reg32 offset="0x0002C" name="POST_DIV"/>
823 <reg32 offset="0x00030" name="POST_DIV_MUX"/>
824 <reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
825 <reg32 offset="0x00038" name="CLK_ENABLE1"/>
826 <reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
827 <reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
828 <reg32 offset="0x00044" name="PLL_EN"/>
829 <reg32 offset="0x00048" name="PLL_IVCO"/>
830 <reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
831 <reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
832 <reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
833 <reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
834 <reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
835 <reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
836 <reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
837 <reg32 offset="0x00064" name="CMN_RSVD0"/>
838 <reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
839 <reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
840 <reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
841 <reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
842 <reg32 offset="0x00070" name="BG_TRIM"/>
843 <reg32 offset="0x00074" name="CLK_EP_DIV"/>
844 <reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
845 <reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
846 <reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
847 <reg32 offset="0x00080" name="CMN_RSVD1"/>
848 <reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
849 <reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
850 <reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
851 <reg32 offset="0x0008C" name="CMN_RSVD2"/>
852 <reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
853 <reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
854 <reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
855 <reg32 offset="0x00098" name="CMN_RSVD3"/>
856 <reg32 offset="0x0009C" name="PLL_CNTRL"/>
857 <reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
858 <reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
859 <reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
860 <reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
861 <reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
862 <reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
863 <reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
864 <reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
865 <reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
866 <reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
867 <reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
868 <reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
869 <reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
870 <reg32 offset="0x000D0" name="DEC_START_MODE0"/>
871 <reg32 offset="0x000D4" name="DEC_START_MODE1"/>
872 <reg32 offset="0x000D8" name="DEC_START_MODE2"/>
873 <reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
874 <reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
875 <reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
876 <reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
877 <reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
878 <reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
879 <reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
880 <reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
881 <reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
882 <reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
883 <reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
884 <reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
885 <reg32 offset="0x000FC" name="CMN_RSVD4"/>
886 <reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
887 <reg32 offset="0x00104" name="INTEGLOOP_EN"/>
888 <reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
889 <reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
890 <reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
891 <reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
892 <reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
893 <reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
894 <reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
895 <reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
896 <reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
897 <reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
898 <reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
899 <reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
900 <reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
901 <reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
902 <reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
903 <reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
904 <reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
905 <reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
906 <reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
907 <reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
908 <reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
909 <reg32 offset="0x0014C" name="SAR"/>
910 <reg32 offset="0x00150" name="SAR_CLK"/>
911 <reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
912 <reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
913 <reg32 offset="0x0015C" name="CMN_STATUS"/>
914 <reg32 offset="0x00160" name="RESET_SM_STATUS"/>
915 <reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
916 <reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
917 <reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
918 <reg32 offset="0x00170" name="BG_CTRL"/>
919 <reg32 offset="0x00174" name="CLK_SELECT"/>
920 <reg32 offset="0x00178" name="HSCLK_SEL"/>
921 <reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
922 <reg32 offset="0x00180" name="PLL_ANALOG"/>
923 <reg32 offset="0x00184" name="CORECLK_DIV"/>
924 <reg32 offset="0x00188" name="SW_RESET"/>
925 <reg32 offset="0x0018C" name="CORE_CLK_EN"/>
926 <reg32 offset="0x00190" name="C_READY_STATUS"/>
927 <reg32 offset="0x00194" name="CMN_CONFIG"/>
928 <reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
929 <reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
930 <reg32 offset="0x001A0" name="DEBUG_BUS0"/>
931 <reg32 offset="0x001A4" name="DEBUG_BUS1"/>
932 <reg32 offset="0x001A8" name="DEBUG_BUS2"/>
933 <reg32 offset="0x001AC" name="DEBUG_BUS3"/>
934 <reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
935 <reg32 offset="0x001B4" name="CMN_MISC1"/>
936 <reg32 offset="0x001B8" name="CMN_MISC2"/>
937 <reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
938 <reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
939 <reg32 offset="0x001C4" name="CMN_RSVD5"/>
944 <reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
945 <reg32 offset="0x00004" name="BIST_INVERT"/>
946 <reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
947 <reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
948 <reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
949 <reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
950 <reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
951 <reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
952 <reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
953 <reg32 offset="0x00024" name="HP_PD_ENABLES"/>
954 <reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
955 <reg32 offset="0x0002C" name="TX_DRV_LVL"/>
956 <reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
957 <reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
958 <reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
959 <reg32 offset="0x0003C" name="TX_BAND"/>
960 <reg32 offset="0x00040" name="SLEW_CNTL"/>
961 <reg32 offset="0x00044" name="INTERFACE_SELECT"/>
962 <reg32 offset="0x00048" name="LPB_EN"/>
963 <reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
964 <reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
965 <reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
966 <reg32 offset="0x00058" name="PERL_LENGTH1"/>
967 <reg32 offset="0x0005C" name="PERL_LENGTH2"/>
968 <reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
969 <reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
970 <reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
971 <reg32 offset="0x0006C" name="TX_POL_INV"/>
972 <reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
973 <reg32 offset="0x00074" name="BIST_PATTERN1"/>
974 <reg32 offset="0x00078" name="BIST_PATTERN2"/>
975 <reg32 offset="0x0007C" name="BIST_PATTERN3"/>
976 <reg32 offset="0x00080" name="BIST_PATTERN4"/>
977 <reg32 offset="0x00084" name="BIST_PATTERN5"/>
978 <reg32 offset="0x00088" name="BIST_PATTERN6"/>
979 <reg32 offset="0x0008C" name="BIST_PATTERN7"/>
980 <reg32 offset="0x00090" name="BIST_PATTERN8"/>
981 <reg32 offset="0x00094" name="LANE_MODE"/>
982 <reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
983 <reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
984 <reg32 offset="0x000A0" name="ATB_SEL1"/>
985 <reg32 offset="0x000A4" name="ATB_SEL2"/>
986 <reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
987 <reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
988 <reg32 offset="0x000B0" name="PRBS_SEED1"/>
989 <reg32 offset="0x000B4" name="PRBS_SEED2"/>
990 <reg32 offset="0x000B8" name="PRBS_SEED3"/>
991 <reg32 offset="0x000BC" name="PRBS_SEED4"/>
992 <reg32 offset="0x000C0" name="RESET_GEN"/>
993 <reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
994 <reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
995 <reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
996 <reg32 offset="0x000D0" name="PWM_CTRL"/>
997 <reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
998 <reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
999 <reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
1000 <reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
1001 <reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
1002 <reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
1003 <reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
1004 <reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
1005 <reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
1006 <reg32 offset="0x000F8" name="VMODE_CTRL1"/>
1007 <reg32 offset="0x000FC" name="VMODE_CTRL2"/>
1008 <reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
1009 <reg32 offset="0x00104" name="BIST_STATUS"/>
1010 <reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
1011 <reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
1012 <reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
1016 <reg32 offset="0x00000" name="CFG"/>
1017 <reg32 offset="0x00004" name="PD_CTL"/>
1018 <reg32 offset="0x00010" name="MODE"/>
1019 <reg32 offset="0x0005C" name="CLOCK"/>
1020 <reg32 offset="0x00068" name="CMN_CTRL"/>
1021 <reg32 offset="0x000B4" name="STATUS"/>
1025 <reg32 offset="0x0000" name="ATB_SEL1"/>
1026 <reg32 offset="0x0004" name="ATB_SEL2"/>
1027 <reg32 offset="0x0008" name="FREQ_UPDATE"/>
1028 <reg32 offset="0x000C" name="BG_TIMER"/>
1029 <reg32 offset="0x0010" name="SSC_EN_CENTER"/>
1030 <reg32 offset="0x0014" name="SSC_ADJ_PER1"/>
1031 <reg32 offset="0x0018" name="SSC_ADJ_PER2"/>
1032 <reg32 offset="0x001C" name="SSC_PER1"/>
1033 <reg32 offset="0x0020" name="SSC_PER2"/>
1034 <reg32 offset="0x0024" name="SSC_STEP_SIZE1"/>
1035 <reg32 offset="0x0028" name="SSC_STEP_SIZE2"/>
1036 <reg32 offset="0x002C" name="POST_DIV"/>
1037 <reg32 offset="0x0030" name="POST_DIV_MUX"/>
1038 <reg32 offset="0x0034" name="BIAS_EN_CLKBUFLR_EN"/>
1039 <reg32 offset="0x0038" name="CLK_ENABLE1"/>
1040 <reg32 offset="0x003C" name="SYS_CLK_CTRL"/>
1041 <reg32 offset="0x0040" name="SYSCLK_BUF_ENABLE"/>
1042 <reg32 offset="0x0044" name="PLL_EN"/>
1043 <reg32 offset="0x0048" name="PLL_IVCO"/>
1044 <reg32 offset="0x004C" name="CMN_IETRIM"/>
1045 <reg32 offset="0x0050" name="CMN_IPTRIM"/>
1046 <reg32 offset="0x0060" name="CP_CTRL_MODE0"/>
1047 <reg32 offset="0x0064" name="CP_CTRL_MODE1"/>
1048 <reg32 offset="0x0068" name="PLL_RCTRL_MODE0"/>
1049 <reg32 offset="0x006C" name="PLL_RCTRL_MODE1"/>
1050 <reg32 offset="0x0070" name="PLL_CCTRL_MODE0"/>
1051 <reg32 offset="0x0074" name="PLL_CCTRL_MODE1"/>
1052 <reg32 offset="0x0078" name="PLL_CNTRL"/>
1053 <reg32 offset="0x007C" name="BIAS_EN_CTRL_BY_PSM"/>
1054 <reg32 offset="0x0080" name="SYSCLK_EN_SEL"/>
1055 <reg32 offset="0x0084" name="CML_SYSCLK_SEL"/>
1056 <reg32 offset="0x0088" name="RESETSM_CNTRL"/>
1057 <reg32 offset="0x008C" name="RESETSM_CNTRL2"/>
1058 <reg32 offset="0x0090" name="LOCK_CMP_EN"/>
1059 <reg32 offset="0x0094" name="LOCK_CMP_CFG"/>
1060 <reg32 offset="0x0098" name="LOCK_CMP1_MODE0"/>
1061 <reg32 offset="0x009C" name="LOCK_CMP2_MODE0"/>
1062 <reg32 offset="0x00A0" name="LOCK_CMP3_MODE0"/>
1063 <reg32 offset="0x00B0" name="DEC_START_MODE0"/>
1064 <reg32 offset="0x00B4" name="DEC_START_MODE1"/>
1065 <reg32 offset="0x00B8" name="DIV_FRAC_START1_MODE0"/>
1066 <reg32 offset="0x00BC" name="DIV_FRAC_START2_MODE0"/>
1067 <reg32 offset="0x00C0" name="DIV_FRAC_START3_MODE0"/>
1068 <reg32 offset="0x00C4" name="DIV_FRAC_START1_MODE1"/>
1069 <reg32 offset="0x00C8" name="DIV_FRAC_START2_MODE1"/>
1070 <reg32 offset="0x00CC" name="DIV_FRAC_START3_MODE1"/>
1071 <reg32 offset="0x00D0" name="INTEGLOOP_INITVAL"/>
1072 <reg32 offset="0x00D4" name="INTEGLOOP_EN"/>
1073 <reg32 offset="0x00D8" name="INTEGLOOP_GAIN0_MODE0"/>
1074 <reg32 offset="0x00DC" name="INTEGLOOP_GAIN1_MODE0"/>
1075 <reg32 offset="0x00E0" name="INTEGLOOP_GAIN0_MODE1"/>
1076 <reg32 offset="0x00E4" name="INTEGLOOP_GAIN1_MODE1"/>
1077 <reg32 offset="0x00E8" name="VCOCAL_DEADMAN_CTRL"/>
1078 <reg32 offset="0x00EC" name="VCO_TUNE_CTRL"/>
1079 <reg32 offset="0x00F0" name="VCO_TUNE_MAP"/>
1080 <reg32 offset="0x0124" name="CMN_STATUS"/>
1081 <reg32 offset="0x0128" name="RESET_SM_STATUS"/>
1082 <reg32 offset="0x0138" name="CLK_SEL"/>
1083 <reg32 offset="0x013C" name="HSCLK_SEL"/>
1084 <reg32 offset="0x0148" name="CORECLK_DIV_MODE0"/>
1085 <reg32 offset="0x0150" name="SW_RESET"/>
1086 <reg32 offset="0x0154" name="CORE_CLK_EN"/>
1087 <reg32 offset="0x0158" name="C_READY_STATUS"/>
1088 <reg32 offset="0x015C" name="CMN_CONFIG"/>
1089 <reg32 offset="0x0164" name="SVS_MODE_CLK_SEL"/>
1093 <reg32 offset="0x0000" name="EMP_POST1_LVL"/>
1094 <reg32 offset="0x0008" name="INTERFACE_SELECT_TX_BAND"/>
1095 <reg32 offset="0x000C" name="CLKBUF_TERM_ENABLE"/>
1096 <reg32 offset="0x0014" name="DRV_LVL_RES_CODE_OFFSET"/>
1097 <reg32 offset="0x0018" name="DRV_LVL"/>
1098 <reg32 offset="0x001C" name="LANE_CONFIG"/>
1099 <reg32 offset="0x0024" name="PRE_DRIVER_1"/>
1100 <reg32 offset="0x0028" name="PRE_DRIVER_2"/>
1101 <reg32 offset="0x002C" name="LANE_MODE"/>