Lines Matching +full:0 +full:x000a8
8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL_0"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
18 <reg32 offset="0x00028" name="CTRL_1"/>
19 <reg32 offset="0x0002c" name="CTRL_2"/>
20 <reg32 offset="0x00030" name="CTRL_3"/>
21 <reg32 offset="0x00034" name="LANE_CFG0"/>
22 <reg32 offset="0x00038" name="LANE_CFG1"/>
23 <reg32 offset="0x0003c" name="PLL_CNTRL"/>
24 <reg32 offset="0x00040" name="DPHY_SOT"/>
25 <reg32 offset="0x000a0" name="LANE_CTRL0"/>
26 <reg32 offset="0x000a4" name="LANE_CTRL1"/>
27 <reg32 offset="0x000a8" name="LANE_CTRL2"/>
28 <reg32 offset="0x000ac" name="LANE_CTRL3"/>
29 <reg32 offset="0x000b0" name="LANE_CTRL4"/>
30 <reg32 offset="0x000b4" name="TIMING_CTRL_0"/>
31 <reg32 offset="0x000b8" name="TIMING_CTRL_1"/>
32 <reg32 offset="0x000bc" name="TIMING_CTRL_2"/>
33 <reg32 offset="0x000c0" name="TIMING_CTRL_3"/>
34 <reg32 offset="0x000c4" name="TIMING_CTRL_4"/>
35 <reg32 offset="0x000c8" name="TIMING_CTRL_5"/>
36 <reg32 offset="0x000cc" name="TIMING_CTRL_6"/>
37 <reg32 offset="0x000d0" name="TIMING_CTRL_7"/>
38 <reg32 offset="0x000d4" name="TIMING_CTRL_8"/>
39 <reg32 offset="0x000d8" name="TIMING_CTRL_9"/>
40 <reg32 offset="0x000dc" name="TIMING_CTRL_10"/>
41 <reg32 offset="0x000e0" name="TIMING_CTRL_11"/>
42 <reg32 offset="0x000e4" name="TIMING_CTRL_12"/>
43 <reg32 offset="0x000e8" name="TIMING_CTRL_13"/>
44 <reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/>
45 <reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/>
46 <reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/>
47 <reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/>
48 <reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/>
49 <reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/>
50 <reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/>
51 <reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/>
52 <reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/>
53 <reg32 offset="0x00110" name="VREG_CTRL_1"/>
54 <reg32 offset="0x00114" name="CTRL_4"/>
55 <reg32 offset="0x00128" name="GLBL_DIGTOP_SPARE4"/>
56 <reg32 offset="0x00140" name="PHY_STATUS"/>
57 <reg32 offset="0x00148" name="LANE_STATUS0"/>
58 <reg32 offset="0x0014c" name="LANE_STATUS1"/>
59 <reg32 offset="0x001ac" name="GLBL_DIGTOP_SPARE10"/>
63 <array offset="0x00000" name="LN" length="5" stride="0x80">
64 <reg32 offset="0x00" name="CFG0"/>
65 <reg32 offset="0x04" name="CFG1"/>
66 <reg32 offset="0x08" name="CFG2"/>
67 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
68 <reg32 offset="0x10" name="PIN_SWAP"/>
69 <reg32 offset="0x14" name="LPRX_CTRL"/>
70 <reg32 offset="0x18" name="TX_DCTRL"/>
75 <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
76 <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
77 <reg32 offset="0x0008" name="INT_LOOP_SETTINGS"/>
78 <reg32 offset="0x000c" name="INT_LOOP_SETTINGS_TWO"/>
79 <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
80 <reg32 offset="0x0014" name="ANALOG_CONTROLS_FOUR"/>
81 <reg32 offset="0x0018" name="ANALOG_CONTROLS_FIVE"/>
82 <reg32 offset="0x001c" name="INT_LOOP_CONTROLS"/>
83 <reg32 offset="0x0020" name="DSM_DIVIDER"/>
84 <reg32 offset="0x0024" name="FEEDBACK_DIVIDER"/>
85 <reg32 offset="0x0028" name="SYSTEM_MUXES"/>
86 <reg32 offset="0x002c" name="FREQ_UPDATE_CONTROL_OVERRIDES"/>
87 <reg32 offset="0x0030" name="CMODE"/>
88 <reg32 offset="0x0034" name="PSM_CTRL"/>
89 <reg32 offset="0x0038" name="RSM_CTRL"/>
90 <reg32 offset="0x003c" name="VCO_TUNE_MAP"/>
91 <reg32 offset="0x0040" name="PLL_CNTRL"/>
92 <reg32 offset="0x0044" name="CALIBRATION_SETTINGS"/>
93 <reg32 offset="0x0048" name="BAND_SEL_CAL_TIMER_LOW"/>
94 <reg32 offset="0x004c" name="BAND_SEL_CAL_TIMER_HIGH"/>
95 <reg32 offset="0x0050" name="BAND_SEL_CAL_SETTINGS"/>
96 <reg32 offset="0x0054" name="BAND_SEL_MIN"/>
97 <reg32 offset="0x0058" name="BAND_SEL_MAX"/>
98 <reg32 offset="0x005c" name="BAND_SEL_PFILT"/>
99 <reg32 offset="0x0060" name="BAND_SEL_IFILT"/>
100 <reg32 offset="0x0064" name="BAND_SEL_CAL_SETTINGS_TWO"/>
101 <reg32 offset="0x0068" name="BAND_SEL_CAL_SETTINGS_THREE"/>
102 <reg32 offset="0x006c" name="BAND_SEL_CAL_SETTINGS_FOUR"/>
103 <reg32 offset="0x0070" name="BAND_SEL_ICODE_HIGH"/>
104 <reg32 offset="0x0074" name="BAND_SEL_ICODE_LOW"/>
105 <reg32 offset="0x0078" name="FREQ_DETECT_SETTINGS_ONE"/>
106 <reg32 offset="0x007c" name="FREQ_DETECT_THRESH"/>
107 <reg32 offset="0x0080" name="FREQ_DET_REFCLK_HIGH"/>
108 <reg32 offset="0x0084" name="FREQ_DET_REFCLK_LOW"/>
109 <reg32 offset="0x0088" name="FREQ_DET_PLLCLK_HIGH"/>
110 <reg32 offset="0x008c" name="FREQ_DET_PLLCLK_LOW"/>
111 <reg32 offset="0x0090" name="PFILT"/>
112 <reg32 offset="0x0094" name="IFILT"/>
113 <reg32 offset="0x0098" name="PLL_GAIN"/>
114 <reg32 offset="0x009c" name="ICODE_LOW"/>
115 <reg32 offset="0x00a0" name="ICODE_HIGH"/>
116 <reg32 offset="0x00a4" name="LOCKDET"/>
117 <reg32 offset="0x00a8" name="OUTDIV"/>
118 <reg32 offset="0x00ac" name="FASTLOCK_CONTROL"/>
119 <reg32 offset="0x00b0" name="PASS_OUT_OVERRIDE_ONE"/>
120 <reg32 offset="0x00b4" name="PASS_OUT_OVERRIDE_TWO"/>
121 <reg32 offset="0x00b8" name="CORE_OVERRIDE"/>
122 <reg32 offset="0x00bc" name="CORE_INPUT_OVERRIDE"/>
123 <reg32 offset="0x00c0" name="RATE_CHANGE"/>
124 <reg32 offset="0x00c4" name="PLL_DIGITAL_TIMERS"/>
125 <reg32 offset="0x00c8" name="PLL_DIGITAL_TIMERS_TWO"/>
126 <reg32 offset="0x00cc" name="DECIMAL_DIV_START"/>
127 <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW"/>
128 <reg32 offset="0x00d4" name="FRAC_DIV_START_MID"/>
129 <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH"/>
130 <reg32 offset="0x00dc" name="DEC_FRAC_MUXES"/>
131 <reg32 offset="0x00e0" name="DECIMAL_DIV_START_1"/>
132 <reg32 offset="0x00e4" name="FRAC_DIV_START_LOW_1"/>
133 <reg32 offset="0x00e8" name="FRAC_DIV_START_MID_1"/>
134 <reg32 offset="0x00ec" name="FRAC_DIV_START_HIGH_1"/>
135 <reg32 offset="0x00f0" name="DECIMAL_DIV_START_2"/>
136 <reg32 offset="0x00f4" name="FRAC_DIV_START_LOW_2"/>
137 <reg32 offset="0x00f8" name="FRAC_DIV_START_MID_2"/>
138 <reg32 offset="0x00fc" name="FRAC_DIV_START_HIGH_2"/>
139 <reg32 offset="0x0100" name="MASH_CONTROL"/>
140 <reg32 offset="0x0104" name="SSC_STEPSIZE_LOW"/>
141 <reg32 offset="0x0108" name="SSC_STEPSIZE_HIGH"/>
142 <reg32 offset="0x010c" name="SSC_DIV_PER_LOW"/>
143 <reg32 offset="0x0110" name="SSC_DIV_PER_HIGH"/>
144 <reg32 offset="0x0114" name="SSC_ADJPER_LOW"/>
145 <reg32 offset="0x0118" name="SSC_ADJPER_HIGH"/>
146 <reg32 offset="0x011c" name="SSC_MUX_CONTROL"/>
147 <reg32 offset="0x0120" name="SSC_STEPSIZE_LOW_1"/>
148 <reg32 offset="0x0124" name="SSC_STEPSIZE_HIGH_1"/>
149 <reg32 offset="0x0128" name="SSC_DIV_PER_LOW_1"/>
150 <reg32 offset="0x012c" name="SSC_DIV_PER_HIGH_1"/>
151 <reg32 offset="0x0130" name="SSC_ADJPER_LOW_1"/>
152 <reg32 offset="0x0134" name="SSC_ADJPER_HIGH_1"/>
153 <reg32 offset="0x0138" name="SSC_STEPSIZE_LOW_2"/>
154 <reg32 offset="0x013c" name="SSC_STEPSIZE_HIGH_2"/>
155 <reg32 offset="0x0140" name="SSC_DIV_PER_LOW_2"/>
156 <reg32 offset="0x0144" name="SSC_DIV_PER_HIGH_2"/>
157 <reg32 offset="0x0148" name="SSC_ADJPER_LOW_2"/>
158 <reg32 offset="0x014c" name="SSC_ADJPER_HIGH_2"/>
159 <reg32 offset="0x0150" name="SSC_CONTROL"/>
160 <reg32 offset="0x0154" name="PLL_OUTDIV_RATE"/>
161 <reg32 offset="0x0158" name="PLL_LOCKDET_RATE_1"/>
162 <reg32 offset="0x015c" name="PLL_LOCKDET_RATE_2"/>
163 <reg32 offset="0x0160" name="PLL_PROP_GAIN_RATE_1"/>
164 <reg32 offset="0x0164" name="PLL_PROP_GAIN_RATE_2"/>
165 <reg32 offset="0x0168" name="PLL_BAND_SEL_RATE_1"/>
166 <reg32 offset="0x016c" name="PLL_BAND_SEL_RATE_2"/>
167 <reg32 offset="0x0170" name="PLL_INT_GAIN_IFILT_BAND_1"/>
168 <reg32 offset="0x0174" name="PLL_INT_GAIN_IFILT_BAND_2"/>
169 <reg32 offset="0x0178" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
170 <reg32 offset="0x017c" name="PLL_FL_INT_GAIN_PFILT_BAND_2"/>
171 <reg32 offset="0x0180" name="PLL_FASTLOCK_EN_BAND"/>
172 <reg32 offset="0x0184" name="FREQ_TUNE_ACCUM_INIT_MID"/>
173 <reg32 offset="0x0188" name="FREQ_TUNE_ACCUM_INIT_HIGH"/>
174 <reg32 offset="0x018c" name="FREQ_TUNE_ACCUM_INIT_MUX"/>
175 <reg32 offset="0x0190" name="PLL_LOCK_OVERRIDE"/>
176 <reg32 offset="0x0194" name="PLL_LOCK_DELAY"/>
177 <reg32 offset="0x0198" name="PLL_LOCK_MIN_DELAY"/>
178 <reg32 offset="0x019c" name="CLOCK_INVERTERS"/>
179 <reg32 offset="0x01a0" name="SPARE_AND_JPC_OVERRIDES"/>
180 <reg32 offset="0x01a4" name="BIAS_CONTROL_1"/>
181 <reg32 offset="0x01a8" name="BIAS_CONTROL_2"/>
182 <reg32 offset="0x01ac" name="ALOG_OBSV_BUS_CTRL_1"/>
183 <reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
184 <reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
185 <reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
186 <reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
187 <reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
188 <reg32 offset="0x01c4" name="FD_OUT_LOW"/>
189 <reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
190 <reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
191 <reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
192 <reg32 offset="0x01d4" name="FLL_CONFIG"/>
193 <reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>
194 <reg32 offset="0x01dc" name="FLL_CODE0"/>
195 <reg32 offset="0x01e0" name="FLL_CODE1"/>
196 <reg32 offset="0x01e4" name="FLL_GAIN0"/>
197 <reg32 offset="0x01e8" name="FLL_GAIN1"/>
198 <reg32 offset="0x01ec" name="SW_RESET"/>
199 <reg32 offset="0x01f0" name="FAST_PWRUP"/>
200 <reg32 offset="0x01f4" name="LOCKTIME0"/>
201 <reg32 offset="0x01f8" name="LOCKTIME1"/>
202 <reg32 offset="0x01fc" name="DEBUG_BUS_SEL"/>
203 <reg32 offset="0x0200" name="DEBUG_BUS0"/>
204 <reg32 offset="0x0204" name="DEBUG_BUS1"/>
205 <reg32 offset="0x0208" name="DEBUG_BUS2"/>
206 <reg32 offset="0x020c" name="DEBUG_BUS3"/>
207 <reg32 offset="0x0210" name="ANALOG_FLL_CONTROL_OVERRIDES"/>
208 <reg32 offset="0x0214" name="VCO_CONFIG"/>
209 <reg32 offset="0x0218" name="VCO_CAL_CODE1_MODE0_STATUS"/>
210 <reg32 offset="0x021c" name="VCO_CAL_CODE1_MODE1_STATUS"/>
211 <reg32 offset="0x0220" name="RESET_SM_STATUS"/>
212 <reg32 offset="0x0224" name="TDC_OFFSET"/>
213 <reg32 offset="0x0228" name="PS3_PWRDOWN_CONTROLS"/>
214 <reg32 offset="0x022c" name="PS4_PWRDOWN_CONTROLS"/>
215 <reg32 offset="0x0230" name="PLL_RST_CONTROLS"/>
216 <reg32 offset="0x0234" name="GEAR_BAND_SELECT_CONTROLS"/>
217 <reg32 offset="0x0238" name="PSM_CLK_CONTROLS"/>
218 <reg32 offset="0x023c" name="SYSTEM_MUXES_2"/>
219 <reg32 offset="0x0240" name="VCO_CONFIG_1"/>
220 <reg32 offset="0x0244" name="VCO_CONFIG_2"/>
221 <reg32 offset="0x0248" name="CLOCK_INVERTERS_1"/>
222 <reg32 offset="0x024c" name="CLOCK_INVERTERS_2"/>
223 <reg32 offset="0x0250" name="CMODE_1"/>
224 <reg32 offset="0x0254" name="CMODE_2"/>
225 <reg32 offset="0x0258" name="ANALOG_CONTROLS_FIVE_1"/>
226 <reg32 offset="0x025c" name="ANALOG_CONTROLS_FIVE_2"/>
227 <reg32 offset="0x0260" name="PERF_OPTIMIZE"/>