Lines Matching +full:name +full:-
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
7 <domain name="DSI" width="32">
8 <enum name="dsi_traffic_mode">
9 <value name="NON_BURST_SYNCH_PULSE" value="0"/>
10 <value name="NON_BURST_SYNCH_EVENT" value="1"/>
11 <value name="BURST_MODE" value="2"/>
13 <enum name="dsi_vid_dst_format">
14 <value name="VID_DST_FORMAT_RGB565" value="0"/>
15 <value name="VID_DST_FORMAT_RGB666" value="1"/>
16 <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
17 <value name="VID_DST_FORMAT_RGB888" value="3"/>
19 <enum name="dsi_rgb_swap">
20 <value name="SWAP_RGB" value="0"/>
21 <value name="SWAP_RBG" value="1"/>
22 <value name="SWAP_BGR" value="2"/>
23 <value name="SWAP_BRG" value="3"/>
24 <value name="SWAP_GRB" value="4"/>
25 <value name="SWAP_GBR" value="5"/>
27 <enum name="dsi_cmd_trigger">
28 <value name="TRIGGER_NONE" value="0"/>
29 <value name="TRIGGER_SEOF" value="1"/>
30 <value name="TRIGGER_TE" value="2"/>
31 <value name="TRIGGER_SW" value="4"/>
32 <value name="TRIGGER_SW_SEOF" value="5"/>
33 <value name="TRIGGER_SW_TE" value="6"/>
35 <enum name="dsi_cmd_dst_format">
36 <value name="CMD_DST_FORMAT_RGB111" value="0"/>
37 <value name="CMD_DST_FORMAT_RGB332" value="3"/>
38 <value name="CMD_DST_FORMAT_RGB444" value="4"/>
39 <value name="CMD_DST_FORMAT_RGB565" value="6"/>
40 <value name="CMD_DST_FORMAT_RGB666" value="7"/>
41 <value name="CMD_DST_FORMAT_RGB888" value="8"/>
43 <enum name="dsi_lane_swap">
44 <value name="LANE_SWAP_0123" value="0"/>
45 <value name="LANE_SWAP_3012" value="1"/>
46 <value name="LANE_SWAP_2301" value="2"/>
47 <value name="LANE_SWAP_1230" value="3"/>
48 <value name="LANE_SWAP_0321" value="4"/>
49 <value name="LANE_SWAP_1032" value="5"/>
50 <value name="LANE_SWAP_2103" value="6"/>
51 <value name="LANE_SWAP_3210" value="7"/>
53 <enum name="video_config_bpp">
54 <value name="VIDEO_CONFIG_18BPP" value="0"/>
55 <value name="VIDEO_CONFIG_24BPP" value="1"/>
57 <enum name="video_pattern_sel">
58 <value name="VID_PRBS" value="0"/>
59 <value name="VID_INCREMENTAL" value="1"/>
60 <value name="VID_FIXED" value="2"/>
61 <value name="VID_MDSS_GENERAL_PATTERN" value="3"/>
63 <enum name="cmd_mdp_stream0_pattern_sel">
64 <value name="CMD_MDP_PRBS" value="0"/>
65 <value name="CMD_MDP_INCREMENTAL" value="1"/>
66 <value name="CMD_MDP_FIXED" value="2"/>
67 <value name="CMD_MDP_MDSS_GENERAL_PATTERN" value="3"/>
69 <enum name="cmd_dma_pattern_sel">
70 <value name="CMD_DMA_PRBS" value="0"/>
71 <value name="CMD_DMA_INCREMENTAL" value="1"/>
72 <value name="CMD_DMA_FIXED" value="2"/>
73 <value name="CMD_DMA_CUSTOM_PATTERN_DMA_FIFO" value="3"/>
75 <bitset name="DSI_IRQ">
76 <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
77 <bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
78 <bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
79 <bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
80 <bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
81 <bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
82 <bitfield name="BTA_DONE" pos="20" type="boolean"/>
83 <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
84 <bitfield name="ERROR" pos="24" type="boolean"/>
85 <bitfield name="MASK_ERROR" pos="25" type="boolean"/>
88 <reg32 offset="0x00000" name="6G_HW_VERSION">
89 <bitfield name="MAJOR" low="28" high="31" type="uint"/>
90 <bitfield name="MINOR" low="16" high="27" type="uint"/>
91 <bitfield name="STEP" low="0" high="15" type="uint"/>
94 <reg32 offset="0x00000" name="CTRL">
95 <bitfield name="ENABLE" pos="0" type="boolean"/>
96 <bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
97 <bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>
98 <bitfield name="LANE0" pos="4" type="boolean"/>
99 <bitfield name="LANE1" pos="5" type="boolean"/>
100 <bitfield name="LANE2" pos="6" type="boolean"/>
101 <bitfield name="LANE3" pos="7" type="boolean"/>
102 <bitfield name="CLK_EN" pos="8" type="boolean"/>
103 <bitfield name="ECC_CHECK" pos="20" type="boolean"/>
104 <bitfield name="CRC_CHECK" pos="24" type="boolean"/>
107 <reg32 offset="0x00004" name="STATUS0">
108 <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
109 <bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
110 <bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
111 <bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
112 <bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() -->
113 <bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
116 <reg32 offset="0x00008" name="FIFO_STATUS">
117 <bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
118 <bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>
119 <bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
120 <bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>
121 <bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>
122 <bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>
123 <bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/>
124 <bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/>
125 <bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/>
126 <bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/>
127 <bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/>
128 <bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/>
129 <bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>
130 <bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/>
131 <bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/>
132 <bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/>
133 <bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>
134 <bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/>
135 <bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/>
136 <bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/>
137 <bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>
138 <bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/>
139 <bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/>
140 <bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/>
141 <bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>
143 <reg32 offset="0x0000c" name="VID_CFG0">
144 <bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
145 <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
146 <bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
147 <bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
148 <bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
149 <bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>
150 <bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>
151 <bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>
152 <bitfield name="DATABUS_WIDEN" pos="25" type="boolean"/>
153 <bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
155 <reg32 offset="0x0001c" name="VID_CFG1">
156 <bitfield name="R_SEL" pos="0" type="boolean"/>
157 <bitfield name="G_SEL" pos="4" type="boolean"/>
158 <bitfield name="B_SEL" pos="8" type="boolean"/>
159 <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
161 <reg32 offset="0x00020" name="ACTIVE_H">
162 <bitfield name="START" low="0" high="11" type="uint"/>
163 <bitfield name="END" low="16" high="27" type="uint"/>
165 <reg32 offset="0x00024" name="ACTIVE_V">
166 <bitfield name="START" low="0" high="11" type="uint"/>
167 <bitfield name="END" low="16" high="27" type="uint"/>
169 <reg32 offset="0x00028" name="TOTAL">
170 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
171 <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
173 <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
174 <bitfield name="START" low="0" high="11" type="uint"/>
175 <bitfield name="END" low="16" high="27" type="uint"/>
177 <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
178 <bitfield name="START" low="0" high="11" type="uint"/>
179 <bitfield name="END" low="16" high="27" type="uint"/>
181 <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
182 <bitfield name="START" low="0" high="11" type="uint"/>
183 <bitfield name="END" low="16" high="27" type="uint"/>
186 <reg32 offset="0x00038" name="CMD_DMA_CTRL">
187 <bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
188 <bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
189 <bitfield name="LOW_POWER" pos="26" type="boolean"/>
191 <reg32 offset="0x0003c" name="CMD_CFG0">
192 <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
193 <bitfield name="R_SEL" pos="4" type="boolean"/>
194 <bitfield name="G_SEL" pos="8" type="boolean"/>
195 <bitfield name="B_SEL" pos="12" type="boolean"/>
196 <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
197 <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
199 <reg32 offset="0x00040" name="CMD_CFG1">
200 <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
201 <bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
202 <bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
204 <reg32 offset="0x00044" name="DMA_BASE"/>
205 <reg32 offset="0x00048" name="DMA_LEN"/>
206 <reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
207 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
208 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
209 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
211 <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
212 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
213 <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
215 <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
216 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
217 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
218 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
220 <reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
221 <bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
222 <bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
224 <reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
225 <array offset="0x00068" name="RDBK" length="4" stride="4">
226 <reg32 offset="0x0" name="DATA"/>
228 <reg32 offset="0x00080" name="TRIG_CTRL">
229 <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
230 <bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
231 <bitfield name="STREAM" low="8" high="9" type="uint"/>
232 <bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
233 <bitfield name="TE" pos="31" type="boolean"/>
235 <reg32 offset="0x0008c" name="TRIG_DMA"/>
236 <reg32 offset="0x000b0" name="DLN0_PHY_ERR">
237 <bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
238 <bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>
239 <bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>
240 <bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>
241 <bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>
243 <reg32 offset="0x000b4" name="LP_TIMER_CTRL">
244 <bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
245 <bitfield name="BTA_TO" low="16" high="31" type="uint"/>
247 <reg32 offset="0x000b8" name="HS_TIMER_CTRL">
248 <bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
249 <bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>
250 <bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>
252 <reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
253 <reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
254 <bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
255 <bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>
257 <reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
258 <bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
259 <bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
261 <reg32 offset="0x000a4" name="LANE_STATUS">
262 <bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
263 <bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>
264 <bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>
265 <bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>
266 <bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>
267 <bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>
268 <bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>
269 <bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>
270 <bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>
271 <bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>
272 <bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
274 <reg32 offset="0x000a8" name="LANE_CTRL">
275 <bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
276 <bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
278 <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
279 <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
281 <reg32 offset="0x00108" name="ERR_INT_MASK0"/>
282 <reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
283 <reg32 offset="0x00114" name="RESET"/>
284 <reg32 offset="0x00118" name="CLK_CTRL">
285 <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
286 <bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
287 <bitfield name="PCLK_ON" pos="2" type="boolean"/>
288 <bitfield name="DSICLK_ON" pos="3" type="boolean"/>
289 <bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
290 <bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
291 <bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
293 <reg32 offset="0x0011c" name="CLK_STATUS">
294 <bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
295 <bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>
296 <bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>
297 <bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>
298 <bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>
299 <bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>
300 <bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>
301 <bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>
302 <bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>
303 <bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>
304 <bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>
305 <bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>
306 <bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>
307 <bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>
308 <bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>
309 <bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
311 <reg32 offset="0x00128" name="PHY_RESET">
312 <bitfield name="RESET" pos="0" type="boolean"/>
314 <reg32 offset="0x00160" name="TEST_PATTERN_GEN_VIDEO_INIT_VAL"/>
315 <reg32 offset="0x00198" name="TPG_MAIN_CONTROL">
316 <bitfield name="CHECKERED_RECTANGLE_PATTERN" pos="8" type="boolean"/>
318 <reg32 offset="0x001a0" name="TPG_VIDEO_CONFIG">
319 <bitfield name="BPP" low="0" high="1" type="video_config_bpp"/>
320 <bitfield name="RGB" pos="2" type="boolean"/>
322 <reg32 offset="0x00158" name="TEST_PATTERN_GEN_CTRL">
323 <bitfield name="CMD_DMA_PATTERN_SEL" low="16" high="17" type="cmd_dma_pattern_sel"/>
324 <bitfield name="CMD_MDP_STREAM0_PATTERN_SEL" low="8" high="9" type="cmd_mdp_stream0_pattern_sel"/>
325 <bitfield name="VIDEO_PATTERN_SEL" low="4" high="5" type="video_pattern_sel"/>
326 <bitfield name="TPG_DMA_FIFO_MODE" pos="2" type="boolean"/>
327 <bitfield name="CMD_DMA_TPG_EN" pos="1" type="boolean"/>
328 <bitfield name="EN" pos="0" type="boolean"/>
330 <reg32 offset="0x00168" name="TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0"/>
331 <reg32 offset="0x00180" name="TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER">
332 <bitfield name="SW_TRIGGER" pos="0" type="boolean"/>
334 <reg32 offset="0x0019c" name="TPG_MAIN_CONTROL2">
335 <bitfield name="CMD_MDP0_CHECKERED_RECTANGLE_PATTERN" pos="7" type="boolean"/>
336 <bitfield name="CMD_MDP1_CHECKERED_RECTANGLE_PATTERN" pos="16" type="boolean"/>
337 <bitfield name="CMD_MDP2_CHECKERED_RECTANGLE_PATTERN" pos="25" type="boolean"/>
339 <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
340 <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
342 <reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
343 <bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
344 <bitfield name="R_SEL" pos="4" type="boolean"/>
345 <bitfield name="G_SEL" pos="5" type="boolean"/>
346 <bitfield name="B_SEL" pos="6" type="boolean"/>
347 <bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>
348 <bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>
349 <bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
350 <bitfield name="BURST_MODE" pos="16" type="boolean"/>
351 <bitfield name="DATABUS_WIDEN" pos="20" type="boolean"/>
353 <reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
354 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
355 <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
356 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
358 <reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
359 <bitfield name="COUNT" low="16" high="23" type="uint"/>
360 <bitfield name="CLR" pos="0" type="boolean"/>
362 <reg32 offset="0x001f0" name="VERSION">
363 <bitfield name="MAJOR" low="24" high="31" type="uint"/>
365 <reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
366 <reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
367 <bitfield name="WC" low="16" high="31" type="uint"/>
368 <bitfield name="DATATYPE" low="8" high="13" type="uint"/>
369 <bitfield name="PKT_PER_LINE" low="6" high="7" type="uint"/>
370 <bitfield name="EOL_BYTE_NUM" low="4" high="5" type="uint"/>
371 <bitfield name="EN" pos="0" type="boolean"/>
373 <reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
374 <bitfield name="STREAM1_DATATYPE" low="24" high="29" type="uint"/>
375 <bitfield name="STREAM1_PKT_PER_LINE" low="22" high="23" type="uint"/>
376 <bitfield name="STREAM1_EOL_BYTE_NUM" low="20" high="21" type="uint"/>
377 <bitfield name="STREAM1_EN" pos="16" type="boolean"/>
378 <bitfield name="STREAM0_DATATYPE" low="8" high="13" type="uint"/>
379 <bitfield name="STREAM0_PKT_PER_LINE" low="6" high="7" type="uint"/>
380 <bitfield name="STREAM0_EOL_BYTE_NUM" low="4" high="5" type="uint"/>
381 <bitfield name="STREAM0_EN" pos="0" type="boolean"/>
383 <reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
384 <bitfield name="STREAM1_SLICE_WIDTH" low="16" high="31" type="uint"/>
385 <bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>