Lines Matching +full:name +full:-
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
8 <enum name="vgt_event_type" varset="chip">
9 <value name="VS_DEALLOC" value="0"/>
10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
11 <value name="VS_DONE_TS" value="2"/>
12 <value name="PS_DONE_TS" value="3"/>
17 <value name="CACHE_FLUSH_TS" value="4"/>
18 <value name="CONTEXT_DONE" value="5"/>
19 <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
20 <value name="VIZQUERY_START" value="7" variants="A2XX"/>
21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
22 <value name="VIZQUERY_END" value="8" variants="A2XX"/>
23 <value name="SC_WAIT_WC" value="9" variants="A2XX"/>
24 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
25 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
26 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
28 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
29 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
30 <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
31 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
38 <value name="ZPASS_DONE" value="21"/>
39 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
45 <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
47 <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
48 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
49 <value name="VS_FETCH_DONE" value="27"/>
50 <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
52 <!-- a5xx events -->
53 <value name="WT_DONE_TS" value="8" variants="A5XX-"/>
54 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
55 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
56 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
57 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
58 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
59 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
60 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
61 <value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
67 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
73 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
79 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
91 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
98 <value name="BLIT" value="30" variants="A5XX-"/>
102 fast-clear buffer or LRZ direction.
111 <value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
113 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
114 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
115 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
116 <value name="UNK_40" value="40" variants="A7XX"/>
117 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
118 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
119 <value name="UNK_2C" value="44" variants="A5XX-"/>
120 <value name="UNK_2D" value="45" variants="A5XX-"/>
122 <!-- a6xx events -->
126 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
128 <value name="LABEL" value="63" variants="A6XX-"/>
130 <!-- note, some of these are the same as a6xx, just named differently -->
133 <value name="DUMMY_EVENT" value="1" variants="A7XX"/>
134 <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
135 <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
136 <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
137 <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
138 <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
139 <value name="CCU_RESOLVE" value="30" variants="A7XX"/>
140 <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
141 <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
142 <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
143 <value name="CACHE_RESET" value="48" variants="A7XX"/>
144 <value name="CACHE_CLEAN" value="49" variants="A7XX"/>
145 <!-- TODO: deal with name conflicts with other gens -->
146 <value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
147 <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
150 <enum name="pc_di_primtype">
151 <value name="DI_PT_NONE" value="0"/>
152 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
153 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
154 <value name="DI_PT_LINELIST" value="2"/>
155 <value name="DI_PT_LINESTRIP" value="3"/>
156 <value name="DI_PT_TRILIST" value="4"/>
157 <value name="DI_PT_TRIFAN" value="5"/>
158 <value name="DI_PT_TRISTRIP" value="6"/>
159 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
160 <value name="DI_PT_RECTLIST" value="8"/>
161 <value name="DI_PT_POINTLIST" value="9"/>
162 <value name="DI_PT_LINE_ADJ" value="0xa"/>
163 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
164 <value name="DI_PT_TRI_ADJ" value="0xc"/>
165 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
167 <value name="DI_PT_PATCHES0" value="0x1f"/>
168 <value name="DI_PT_PATCHES1" value="0x20"/>
169 <value name="DI_PT_PATCHES2" value="0x21"/>
170 <value name="DI_PT_PATCHES3" value="0x22"/>
171 <value name="DI_PT_PATCHES4" value="0x23"/>
172 <value name="DI_PT_PATCHES5" value="0x24"/>
173 <value name="DI_PT_PATCHES6" value="0x25"/>
174 <value name="DI_PT_PATCHES7" value="0x26"/>
175 <value name="DI_PT_PATCHES8" value="0x27"/>
176 <value name="DI_PT_PATCHES9" value="0x28"/>
177 <value name="DI_PT_PATCHES10" value="0x29"/>
178 <value name="DI_PT_PATCHES11" value="0x2a"/>
179 <value name="DI_PT_PATCHES12" value="0x2b"/>
180 <value name="DI_PT_PATCHES13" value="0x2c"/>
181 <value name="DI_PT_PATCHES14" value="0x2d"/>
182 <value name="DI_PT_PATCHES15" value="0x2e"/>
183 <value name="DI_PT_PATCHES16" value="0x2f"/>
184 <value name="DI_PT_PATCHES17" value="0x30"/>
185 <value name="DI_PT_PATCHES18" value="0x31"/>
186 <value name="DI_PT_PATCHES19" value="0x32"/>
187 <value name="DI_PT_PATCHES20" value="0x33"/>
188 <value name="DI_PT_PATCHES21" value="0x34"/>
189 <value name="DI_PT_PATCHES22" value="0x35"/>
190 <value name="DI_PT_PATCHES23" value="0x36"/>
191 <value name="DI_PT_PATCHES24" value="0x37"/>
192 <value name="DI_PT_PATCHES25" value="0x38"/>
193 <value name="DI_PT_PATCHES26" value="0x39"/>
194 <value name="DI_PT_PATCHES27" value="0x3a"/>
195 <value name="DI_PT_PATCHES28" value="0x3b"/>
196 <value name="DI_PT_PATCHES29" value="0x3c"/>
197 <value name="DI_PT_PATCHES30" value="0x3d"/>
198 <value name="DI_PT_PATCHES31" value="0x3e"/>
201 <enum name="pc_di_src_sel">
202 <value name="DI_SRC_SEL_DMA" value="0"/>
203 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
204 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
205 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
208 <enum name="pc_di_face_cull_sel">
209 <value name="DI_FACE_CULL_NONE" value="0"/>
210 <value name="DI_FACE_CULL_FETCH" value="1"/>
211 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
212 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
215 <enum name="pc_di_index_size">
216 <value name="INDEX_SIZE_IGN" value="0"/>
217 <value name="INDEX_SIZE_16_BIT" value="0"/>
218 <value name="INDEX_SIZE_32_BIT" value="1"/>
219 <value name="INDEX_SIZE_8_BIT" value="2"/>
220 <value name="INDEX_SIZE_INVALID"/>
223 <enum name="pc_di_vis_cull_mode">
224 <value name="IGNORE_VISIBILITY" value="0"/>
225 <value name="USE_VISIBILITY" value="1"/>
228 <enum name="adreno_pm4_packet_type">
229 <value name="CP_TYPE0_PKT" value="0x00000000"/>
230 <value name="CP_TYPE1_PKT" value="0x40000000"/>
231 <value name="CP_TYPE2_PKT" value="0x80000000"/>
232 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
233 <value name="CP_TYPE4_PKT" value="0x40000000"/>
234 <value name="CP_TYPE7_PKT" value="0x70000000"/>
237 <!--
243 disambiguate the packet-id's that were re-used for different
245 -->
246 <enum name="adreno_pm4_type3_packets" varset="chip">
247 <doc>initialize CP's micro-engine</doc>
248 <value name="CP_ME_INIT" value="0x48"/>
249 <doc>skip N 32-bit words to get to the next packet</doc>
250 <value name="CP_NOP" value="0x10"/>
253 type to determine whether to pre-fetch the IB
255 <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/>
256 <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/>
257 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
263 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
265 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
270 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
272 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
274 <value name="CP_WAIT_REG_EQ" value="0x52"/>
276 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
278 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
280 <!--
283 -->
284 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
286 <value name="CP_REG_RMW" value="0x21"/>
288 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
289 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
291 <value name="CP_REG_TO_MEM" value="0x3e"/>
292 <doc>write N 32-bit words to memory</doc>
293 <value name="CP_MEM_WRITE" value="0x3d"/>
295 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
297 <value name="CP_COND_EXEC" value="0x44"/>
299 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
300 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
302 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
303 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
305 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
307 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
309 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
311 not sure the real name, but this seems to be what is used for
314 <value name="CP_RUN_OPENCL" value="0x31"/>
316 <value name="CP_DRAW_INDX" value="0x22"/>
318 …<value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different…
320 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
322 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
324 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
325 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
326 <value name="CP_SET_STATE" value="0x25"/>
328 <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
329 <doc>load sequencer instruction memory (pointer-based)</doc>
330 <value name="CP_IM_LOAD" value="0x27"/>
332 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
334 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
336 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
338 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
339 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
340 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
341 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
342 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
344 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
346 <value name="CP_INTERRUPT" value="0x40"/>
348 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
350 <!-- For a20x -->
351 <!-- TODO handle variants..
356 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
357 -->
359 <!-- for a22x -->
361 sets draw initiator flags register in PFP, gets bitwise-ORed into
364 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
366 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
368 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
370 <!-- for a3xx -->
372 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
373 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
375 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
377 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
378 <doc>Load a buffer with pre-fetch enabled</doc>
379 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
381 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
384 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
387 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
389 <doc>Record the real-time when this packet is processed by PFP</doc>
390 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
392 <!-- Used to switch GPU between secure and non-secure modes -->
393 <value name="CP_SET_SECURE_MODE" value="0x66"/>
396 <value name="CP_WAIT_FOR_ME" value="0x13"/>
398 <!-- for a4xx -->
408 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
409 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
410 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
411 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
412 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
413 <value name="CP_DRAW_AUTO" value="0x24"/>
420 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
433 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
438 <value name="CP_DRAW_PRED_SET" value="0x4e"/>
442 Write to register with address that does not fit into type-0 pkt
444 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
447 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
450 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
453 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
456 <value name="CP_COND_REG_EXEC" value="0x47"/>
459 <value name="CP_MEM_TO_REG" value="0x42"/>
461 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/>
462 <value name="CP_EXEC_CS" value="0x33"/>
467 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
468 <!-- switches SMMU pagetable, used on a5xx+ only -->
469 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
470 <!-- for a6xx -->
472 <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
474 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/>
475 <!--
478 -->
479 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/>
480 <!-- A5XX Enable yield in RB only -->
481 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
488 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
489 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
490 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
491 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
492 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/>
493 <!-- Enable/Disable/Defer A5x global preemption model -->
494 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
495 <!-- Enable/Disable A5x local preemption model -->
496 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
497 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
498 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/>
499 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
500 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
501 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
502 <!-- check if this works on earlier.. -->
503 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
510 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
512 <!-- Test specified bit in specified register and set predicate -->
513 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
515 <!--
521 -->
522 <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
524 <!--
537 -->
538 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
539 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
540 <!--
545 -->
546 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
548 <!-- internal packets: -->
549 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
550 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
551 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
552 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
553 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
554 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
555 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
556 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
558 <!-- internal jumptable entries on a6xx+, possibly a5xx: -->
560 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
561 <value name="PKT4" value="0x04" variants="A5XX-"/>
562 <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
563 <value name="IN_IB_END" value="0x0a" variants="A6XX-"/>
564 <!-- handles IFPC save/restore -->
565 <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/>
566 <!-- preemption/context-swtich routine -->
567 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
569 <!-- TODO do these exist on A5xx? -->
570 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
571 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
572 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
573 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
574 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
575 <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
576 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/>
577 <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
578 <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
583 <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
584 <!-- Note, kgsl calls this CP_SET_AMBLE: -->
585 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
587 <!--
605 -->
606 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
611 used to loop over bins. There is a fixed-size per-iteration
612 prefix, used to set per-bin state, and then the following IB1
620 <value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
621 <value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
623 <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
624 <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
626 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
627 <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
628 …<value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x…
629 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
630 …<!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for G…
631 <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
633 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
635 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/>
636 <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
637 <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
643 <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
646 Executes an array of fixed-size command buffers where each
648 non-visible draw calls.
650 <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
652 <doc>Reset various on-chip state used for synchronization</doc>
653 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
657 <domain name="CP_LOAD_STATE" width="32">
659 <enum name="adreno_state_block">
660 <value name="SB_VERT_TEX" value="0"/>
661 <value name="SB_VERT_MIPADDR" value="1"/>
662 <value name="SB_FRAG_TEX" value="2"/>
663 <value name="SB_FRAG_MIPADDR" value="3"/>
664 <value name="SB_VERT_SHADER" value="4"/>
665 <value name="SB_GEOM_SHADER" value="5"/>
666 <value name="SB_FRAG_SHADER" value="6"/>
667 <value name="SB_COMPUTE_SHADER" value="7"/>
669 <enum name="adreno_state_type">
670 <value name="ST_SHADER" value="0"/>
671 <value name="ST_CONSTANTS" value="1"/>
673 <enum name="adreno_state_src">
674 <value name="SS_DIRECT" value="0">
677 <value name="SS_INVALID_ALL_IC" value="2"/>
678 <value name="SS_INVALID_PART_IC" value="3"/>
679 <value name="SS_INDIRECT" value="4">
682 <value name="SS_INDIRECT_TCM" value="5"/>
683 <value name="SS_INDIRECT_STM" value="6"/>
685 <reg32 offset="0" name="0">
686 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
687 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
688 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
689 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
691 <reg32 offset="1" name="1">
692 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
693 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
697 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
699 <enum name="a4xx_state_block">
700 <!--
701 unknown: 0x7 and 0xf <- seen in compute shader
708 16 -> vert
709 36 -> tcs
710 56 -> tes
711 76 -> geom
712 96 -> frag
733 -->
734 <value name="SB4_VS_TEX" value="0x0"/>
735 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
736 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
737 <value name="SB4_GS_TEX" value="0x3"/>
738 <value name="SB4_FS_TEX" value="0x4"/>
739 <value name="SB4_CS_TEX" value="0x5"/>
740 <value name="SB4_VS_SHADER" value="0x8"/>
741 <value name="SB4_HS_SHADER" value="0x9"/>
742 <value name="SB4_DS_SHADER" value="0xa"/>
743 <value name="SB4_GS_SHADER" value="0xb"/>
744 <value name="SB4_FS_SHADER" value="0xc"/>
745 <value name="SB4_CS_SHADER" value="0xd"/>
746 <!--
752 -->
753 <value name="SB4_SSBO" value="0xe"/>
754 <value name="SB4_CS_SSBO" value="0xf"/>
756 <enum name="a4xx_state_type">
757 <value name="ST4_SHADER" value="0"/>
758 <value name="ST4_CONSTANTS" value="1"/>
759 <value name="ST4_UBO" value="2"/>
761 <enum name="a4xx_state_src">
762 <value name="SS4_DIRECT" value="0"/>
763 <value name="SS4_INDIRECT" value="2"/>
765 <reg32 offset="0" name="0">
766 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
767 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
768 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
769 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
771 <reg32 offset="1" name="1">
772 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
773 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
775 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
776 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
780 <!-- looks basically same CP_LOAD_STATE4 -->
781 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
783 <enum name="a6xx_state_block">
784 <value name="SB6_VS_TEX" value="0x0"/>
785 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
786 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
787 <value name="SB6_GS_TEX" value="0x3"/>
788 <value name="SB6_FS_TEX" value="0x4"/>
789 <value name="SB6_CS_TEX" value="0x5"/>
790 <value name="SB6_VS_SHADER" value="0x8"/>
791 <value name="SB6_HS_SHADER" value="0x9"/>
792 <value name="SB6_DS_SHADER" value="0xa"/>
793 <value name="SB6_GS_SHADER" value="0xb"/>
794 <value name="SB6_FS_SHADER" value="0xc"/>
795 <value name="SB6_CS_SHADER" value="0xd"/>
796 <value name="SB6_IBO" value="0xe"/>
797 <value name="SB6_CS_IBO" value="0xf"/>
799 <enum name="a6xx_state_type">
800 <value name="ST6_SHADER" value="0"/>
801 <value name="ST6_CONSTANTS" value="1"/>
802 <value name="ST6_UBO" value="2"/>
803 <value name="ST6_IBO" value="3"/>
805 <enum name="a6xx_state_src">
806 <value name="SS6_DIRECT" value="0"/>
807 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
808 <value name="SS6_INDIRECT" value="2"/>
816 <value name="SS6_UBO" value="3"/>
818 <reg32 offset="0" name="0">
819 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
820 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
821 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
822 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
823 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
825 <reg32 offset="1" name="1">
826 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
828 <reg32 offset="2" name="2">
829 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
831 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
834 <bitset name="vgt_draw_initiator" inline="yes">
835 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
836 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
837 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
838 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
839 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
840 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
841 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
842 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
845 <!-- changed on a4xx: -->
846 <enum name="a4xx_index_size">
847 <value name="INDEX4_SIZE_8_BIT" value="0"/>
848 <value name="INDEX4_SIZE_16_BIT" value="1"/>
849 <value name="INDEX4_SIZE_32_BIT" value="2"/>
852 <enum name="a6xx_patch_type">
853 <value name="TESS_QUADS" value="0"/>
854 <value name="TESS_TRIANGLES" value="1"/>
855 <value name="TESS_ISOLINES" value="2"/>
858 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
859 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
860 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
861 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
862 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
863 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
864 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
865 <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
866 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
869 <domain name="CP_DRAW_INDX" width="32">
870 <reg32 offset="0" name="0">
871 <bitfield name="VIZ_QUERY" low="0" high="31"/>
873 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
874 <reg32 offset="2" name="2">
875 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
877 <reg32 offset="3" name="3">
878 <bitfield name="INDX_BASE" low="0" high="31"/>
880 <reg32 offset="4" name="4">
881 <bitfield name="INDX_SIZE" low="0" high="31"/>
885 <domain name="CP_DRAW_INDX_2" width="32">
886 <reg32 offset="0" name="0">
887 <bitfield name="VIZ_QUERY" low="0" high="31"/>
889 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
890 <reg32 offset="2" name="2">
891 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
893 <!-- followed by NUM_INDICES indices.. -->
896 <domain name="CP_DRAW_INDX_OFFSET" width="32">
897 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
898 <reg32 offset="1" name="1">
899 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
901 <reg32 offset="2" name="2">
902 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
904 <reg32 offset="3" name="3">
905 <bitfield name="FIRST_INDX" low="0" high="31"/>
908 <stripe varset="chip" variants="A5XX-">
909 <reg32 offset="4" name="4">
910 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
912 <reg32 offset="5" name="5">
913 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
915 <reg64 offset="4" name="INDX_BASE" type="address"/>
916 <reg32 offset="6" name="6">
917 <!-- max # of elements in index buffer -->
918 <bitfield name="MAX_INDICES" low="0" high="31"/>
922 <reg32 offset="4" name="4">
923 <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
926 <reg32 offset="5" name="5">
927 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
931 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
932 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
934 <reg32 offset="1" name="1">
935 <bitfield name="INDIRECT" low="0" high="31"/>
938 <stripe varset="chip" variants="A5XX-">
939 <reg32 offset="1" name="1">
940 <bitfield name="INDIRECT_LO" low="0" high="31"/>
942 <reg32 offset="2" name="2">
943 <bitfield name="INDIRECT_HI" low="0" high="31"/>
945 <reg64 offset="1" name="INDIRECT" type="address"/>
949 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
950 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
952 <reg32 offset="1" name="1">
953 <bitfield name="INDX_BASE" low="0" high="31"/>
955 <reg32 offset="2" name="2">
956 <!-- max # of bytes in index buffer -->
957 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
959 <reg32 offset="3" name="3">
960 <bitfield name="INDIRECT" low="0" high="31"/>
963 <stripe varset="chip" variants="A5XX-">
964 <reg32 offset="1" name="1">
965 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
967 <reg32 offset="2" name="2">
968 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
970 <reg64 offset="1" name="INDX_BASE" type="address"/>
971 <reg32 offset="3" name="3">
972 <!-- max # of elements in index buffer -->
973 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
975 <reg32 offset="4" name="4">
976 <bitfield name="INDIRECT_LO" low="0" high="31"/>
978 <reg32 offset="5" name="5">
979 <bitfield name="INDIRECT_HI" low="0" high="31"/>
981 <reg64 offset="4" name="INDIRECT" type="address"/>
985 <domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
986 <enum name="a6xx_draw_indirect_opcode">
987 <value name="INDIRECT_OP_NORMAL" value="0x2"/>
988 <value name="INDIRECT_OP_INDEXED" value="0x4"/>
989 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
990 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
992 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
993 <reg32 offset="1" name="1">
994 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
996 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
1000 <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
1002 <reg32 offset="2" name="DRAW_COUNT" type="uint"/>
1004 <reg64 offset="3" name="INDIRECT" type="address"/>
1005 <reg32 offset="5" name="STRIDE" type="uint"/>
1008 <reg64 offset="3" name="INDEX" type="address"/>
1009 <reg32 offset="5" name="MAX_INDICES" type="uint"/>
1010 <reg64 offset="6" name="INDIRECT" type="address"/>
1011 <reg32 offset="8" name="STRIDE" type="uint"/>
1014 <reg64 offset="3" name="INDIRECT" type="address"/>
1015 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
1016 <reg32 offset="7" name="STRIDE" type="uint"/>
1019 <reg64 offset="3" name="INDEX" type="address"/>
1020 <reg32 offset="5" name="MAX_INDICES" type="uint"/>
1021 <reg64 offset="6" name="INDIRECT" type="address"/>
1022 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
1023 <reg32 offset="10" name="STRIDE" type="uint"/>
1027 <domain name="CP_DRAW_AUTO" width="32">
1028 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
1029 <reg32 offset="1" name="1">
1030 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
1032 <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/>
1033 <reg32 offset="4" name="4">
1034 <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/>
1036 <reg32 offset="5" name="5">
1037 <bitfield name="STRIDE" low="0" high="31" type="uint"/>
1041 <domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
1042 <reg32 offset="0" name="0">
1043 <bitfield name="ENABLE" pos="0" type="boolean"/>
1047 <domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
1048 <reg32 offset="0" name="0">
1049 <bitfield name="ENABLE" pos="0" type="boolean"/>
1053 <domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
1054 <enum name="cp_draw_pred_src">
1055 <!--
1056 Sources 1-4 seem to be about combining reading
1058 a DX11-specific optimization (since in DX11 you can only
1060 -->
1061 <value name="PRED_SRC_MEM" value="5">
1063 Read a 64-bit value at the given address and
1068 <enum name="cp_draw_pred_test">
1069 <value name="NE_0_PASS" value="0"/>
1070 <value name="EQ_0_PASS" value="1"/>
1072 <reg32 offset="0" name="0">
1073 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
1074 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
1076 <reg64 offset="1" name="MEM_ADDR" type="address"/>
1079 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
1081 <reg32 offset="0" name="0">
1082 <bitfield name="COUNT" low="0" high="15" type="uint"/>
1083 <bitfield name="DIRTY" pos="16" type="boolean"/>
1084 <bitfield name="DISABLE" pos="17" type="boolean"/>
1085 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
1086 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
1087 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
1088 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
1089 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
1090 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
1092 <reg32 offset="1" name="1">
1093 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
1095 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1096 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
1101 <domain name="CP_SET_BIN" width="32">
1103 <reg32 offset="0" name="0"/>
1104 <reg32 offset="1" name="1">
1105 <bitfield name="X1" low="0" high="15" type="uint"/>
1106 <bitfield name="Y1" low="16" high="31" type="uint"/>
1108 <reg32 offset="2" name="2">
1109 <bitfield name="X2" low="0" high="15" type="uint"/>
1110 <bitfield name="Y2" low="16" high="31" type="uint"/>
1114 <domain name="CP_SET_BIN_DATA" width="32">
1115 <reg32 offset="0" name="0">
1116 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
1117 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
1119 <reg32 offset="1" name="1">
1120 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
1121 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
1125 <domain name="CP_SET_BIN_DATA5" width="32">
1126 <reg32 offset="0" name="0">
1127 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1128 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1129 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1130 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
1132 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1133 <reg32 offset="1" name="1">
1134 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
1136 <reg32 offset="2" name="2">
1137 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
1139 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1140 <reg32 offset="3" name="3">
1141 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
1143 <reg32 offset="4" name="4">
1144 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
1146 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
1147 <reg32 offset="5" name="5">
1148 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
1150 <reg32 offset="6" name="6">
1151 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
1153 <!--
1155 -->
1156 <reg64 offset="7" name="7"/>
1157 <reg64 offset="9" name="9"/>
1160 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
1167 <reg32 offset="0" name="0">
1168 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1169 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1170 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1171 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
1173 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1174 <reg32 offset="1" name="1">
1175 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
1177 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1178 <reg32 offset="2" name="2">
1179 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
1181 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
1182 <reg32 offset="3" name="3">
1183 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
1187 <domain name="CP_REG_RMW" width="32">
1200 <reg32 offset="0" name="0">
1201 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
1202 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
1203 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
1204 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
1205 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
1207 <reg32 offset="1" name="1">
1208 <bitfield name="SRC0" low="0" high="31" type="uint"/>
1210 <reg32 offset="2" name="2">
1211 <bitfield name="SRC1" low="0" high="31" type="uint"/>
1215 <domain name="CP_REG_TO_MEM" width="32">
1216 <reg32 offset="0" name="0">
1217 <bitfield name="REG" low="0" high="17" type="hex"/>
1218 <!-- number of registers/dwords copied is max(CNT, 1). -->
1219 <bitfield name="CNT" low="18" high="29" type="uint"/>
1220 <bitfield name="64B" pos="30" type="boolean"/>
1221 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1223 <reg32 offset="1" name="1">
1224 <bitfield name="DEST" low="0" high="31"/>
1226 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1227 <bitfield name="DEST_HI" low="0" high="31"/>
1231 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
1237 <reg32 offset="0" name="0">
1238 <bitfield name="REG" low="0" high="17" type="hex"/>
1239 <!-- number of registers/dwords copied is max(CNT, 1). -->
1240 <bitfield name="CNT" low="18" high="29" type="uint"/>
1241 <bitfield name="64B" pos="30" type="boolean"/>
1242 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1244 <reg32 offset="1" name="1">
1245 <bitfield name="DEST" low="0" high="31"/>
1247 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1248 <bitfield name="DEST_HI" low="0" high="31"/>
1250 <reg32 offset="3" name="3">
1251 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
1252 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
1254 <!-- followed by an optional identical OFFSET1 dword -->
1257 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
1262 <reg32 offset="0" name="0">
1263 <bitfield name="REG" low="0" high="17" type="hex"/>
1264 <!-- number of registers/dwords copied is max(CNT, 1). -->
1265 <bitfield name="CNT" low="18" high="29" type="uint"/>
1266 <bitfield name="64B" pos="30" type="boolean"/>
1267 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1269 <reg32 offset="1" name="1">
1270 <bitfield name="DEST" low="0" high="31"/>
1272 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1273 <bitfield name="DEST_HI" low="0" high="31"/>
1275 <reg32 offset="3" name="3">
1276 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1278 <reg32 offset="4" name="4">
1279 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1283 <domain name="CP_MEM_TO_REG" width="32">
1284 <reg32 offset="0" name="0">
1285 <bitfield name="REG" low="0" high="17" type="hex"/>
1286 <!-- number of registers/dwords copied is max(CNT, 1). -->
1287 <bitfield name="CNT" low="19" high="29" type="uint"/>
1288 <!-- shift each DWORD left by 2 while copying -->
1289 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1290 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1291 <bitfield name="UNK31" pos="31" type="boolean"/>
1293 <reg32 offset="1" name="1">
1294 <bitfield name="SRC" low="0" high="31"/>
1296 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1297 <bitfield name="SRC_HI" low="0" high="31"/>
1301 <domain name="CP_MEM_TO_MEM" width="32">
1302 <reg32 offset="0" name="0">
1303 <!--
1306 -->
1307 <bitfield name="NEG_A" pos="0" type="boolean"/>
1308 <bitfield name="NEG_B" pos="1" type="boolean"/>
1309 <bitfield name="NEG_C" pos="2" type="boolean"/>
1311 <!-- if set treat src/dst as 64bit values -->
1312 <bitfield name="DOUBLE" pos="29" type="boolean"/>
1313 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1314 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1315 <!-- some other kind of wait -->
1316 <bitfield name="UNK31" pos="31" type="boolean"/>
1318 <!--
1322 to do things like 'result += end - start' (which turns
1325 -->
1328 <domain name="CP_MEMCPY" width="32">
1329 <reg32 offset="0" name="0">
1330 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1332 <reg32 offset="1" name="1">
1333 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1335 <reg32 offset="2" name="2">
1336 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1338 <reg32 offset="3" name="3">
1339 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1341 <reg32 offset="4" name="4">
1342 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1346 <domain name="CP_REG_TO_SCRATCH" width="32">
1347 <reg32 offset="0" name="0">
1348 <bitfield name="REG" low="0" high="17" type="hex"/>
1349 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1350 <!-- number of registers/dwords copied is CNT + 1. -->
1351 <bitfield name="CNT" low="24" high="26" type="uint"/>
1355 <domain name="CP_SCRATCH_TO_REG" width="32">
1356 <reg32 offset="0" name="0">
1357 <bitfield name="REG" low="0" high="17" type="hex"/>
1358 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1359 <bitfield name="UNK18" pos="18" type="boolean"/>
1360 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1361 <!-- number of registers/dwords copied is CNT + 1. -->
1362 <bitfield name="CNT" low="24" high="26" type="uint"/>
1366 <domain name="CP_SCRATCH_WRITE" width="32">
1367 <reg32 offset="0" name="0">
1368 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1370 <!-- followed by one or more DWORDs to write to scratch registers -->
1373 <domain name="CP_MEM_WRITE" width="32">
1374 <reg32 offset="0" name="0">
1375 <bitfield name="ADDR_LO" low="0" high="31"/>
1377 <reg32 offset="1" name="1">
1378 <bitfield name="ADDR_HI" low="0" high="31"/>
1380 <!-- followed by the DWORDs to write -->
1383 <enum name="cp_cond_function">
1384 <value value="0" name="WRITE_ALWAYS"/>
1385 <value value="1" name="WRITE_LT"/>
1386 <value value="2" name="WRITE_LE"/>
1387 <value value="3" name="WRITE_EQ"/>
1388 <value value="4" name="WRITE_NE"/>
1389 <value value="5" name="WRITE_GE"/>
1390 <value value="6" name="WRITE_GT"/>
1393 <domain name="CP_COND_WRITE" width="32">
1394 <reg32 offset="0" name="0">
1395 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1396 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1397 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1399 <reg32 offset="1" name="1">
1400 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1402 <reg32 offset="2" name="2">
1403 <bitfield name="REF" low="0" high="31"/>
1405 <reg32 offset="3" name="3">
1406 <bitfield name="MASK" low="0" high="31"/>
1408 <reg32 offset="4" name="4">
1409 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1411 <reg32 offset="5" name="5">
1412 <bitfield name="WRITE_DATA" low="0" high="31"/>
1416 <enum name="poll_memory_type">
1417 <value value="0" name="POLL_REGISTER"/>
1418 <value value="1" name="POLL_MEMORY"/>
1419 <value value="2" name="POLL_SCRATCH"/>
1420 <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
1423 <domain name="CP_COND_WRITE5" width="32">
1424 <reg32 offset="0" name="0">
1425 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1426 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1427 <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
1428 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1429 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1431 <reg32 offset="1" name="1">
1432 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1434 <reg32 offset="2" name="2">
1435 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1437 <reg32 offset="3" name="3">
1438 <bitfield name="REF" low="0" high="31"/>
1440 <reg32 offset="4" name="4">
1441 <bitfield name="MASK" low="0" high="31"/>
1443 <reg32 offset="5" name="5">
1444 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1446 <reg32 offset="6" name="6">
1447 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1449 <reg32 offset="7" name="7">
1450 <bitfield name="WRITE_DATA" low="0" high="31"/>
1454 <domain name="CP_WAIT_MEM_GTE" width="32">
1459 <reg32 offset="0" name="0">
1460 <!-- Reserved for flags, presumably? Unused in FW -->
1461 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1463 <reg32 offset="1" name="1">
1464 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1466 <reg32 offset="2" name="2">
1467 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1469 <reg32 offset="3" name="3">
1470 <bitfield name="REF" low="0" high="31"/>
1474 <domain name="CP_WAIT_REG_MEM" width="32">
1477 but waits until the comparison is true instead. It busy-loops in
1480 <reg32 offset="0" name="0">
1481 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1482 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1483 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1484 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1486 <reg32 offset="1" name="1">
1487 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1489 <reg32 offset="2" name="2">
1490 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1492 <reg32 offset="3" name="3">
1493 <bitfield name="REF" low="0" high="31"/>
1495 <reg32 offset="4" name="4">
1496 <bitfield name="MASK" low="0" high="31"/>
1498 <reg32 offset="5" name="5">
1499 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1503 <domain name="CP_WAIT_TWO_REGS" width="32">
1507 <reg32 offset="0" name="0">
1508 <bitfield name="REG0" low="0" high="17" type="hex"/>
1510 <reg32 offset="1" name="1">
1511 <bitfield name="REG1" low="0" high="17" type="hex"/>
1513 <reg32 offset="2" name="2">
1514 <bitfield name="REF" low="0" high="31" type="uint"/>
1518 <domain name="CP_DISPATCH_COMPUTE" width="32">
1519 <reg32 offset="0" name="0"/>
1520 <reg32 offset="1" name="1">
1521 <bitfield name="X" low="0" high="31"/>
1523 <reg32 offset="2" name="2">
1524 <bitfield name="Y" low="0" high="31"/>
1526 <reg32 offset="3" name="3">
1527 <bitfield name="Z" low="0" high="31"/>
1531 <domain name="CP_SET_RENDER_MODE" width="32">
1532 <enum name="render_mode_cmd">
1533 <value value="1" name="BYPASS"/>
1534 <value value="2" name="BINNING"/>
1535 <value value="3" name="GMEM"/>
1536 <value value="5" name="BLIT2D"/>
1537 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1538 <value value="7" name="BLIT2DSCALE"/>
1539 <!-- 8 set before going back to BYPASS exiting 2D -->
1540 <value value="8" name="END2D"/>
1542 <reg32 offset="0" name="0">
1543 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1544 <!--
1548 -->
1550 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1551 <reg32 offset="1" name="1">
1552 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1554 <reg32 offset="2" name="2">
1555 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1557 <reg32 offset="3" name="3">
1558 <!--
1561 -->
1562 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1563 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1565 <reg32 offset="4" name="4"/>
1566 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1567 <reg32 offset="5" name="5">
1568 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1570 <reg32 offset="6" name="6">
1571 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1573 <reg32 offset="7" name="7">
1574 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1578 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1579 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1580 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1581 <reg32 offset="0" name="0">
1582 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1584 <reg32 offset="1" name="1">
1585 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1587 <reg32 offset="2" name="2">
1589 <reg32 offset="3" name="3"/>
1590 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1591 <reg32 offset="4" name="4">
1592 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1594 <reg32 offset="5" name="5">
1595 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1597 <reg32 offset="6" name="6">
1598 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1600 <reg32 offset="7" name="7"/>
1603 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1604 <reg32 offset="0" name="0">
1606 <reg32 offset="1" name="1">
1607 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1609 <reg32 offset="2" name="2">
1610 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1614 <domain varset="chip" name="CP_EVENT_WRITE" width="32">
1615 <reg32 offset="0" name="0">
1616 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1617 <!-- when set, write back timestamp instead of value from packet: -->
1618 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1619 <bitfield name="IRQ" pos="31" type="boolean"/>
1621 <!--
1624 -->
1625 <reg32 offset="1" name="1">
1626 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1628 <reg32 offset="2" name="2">
1629 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1631 <reg32 offset="3" name="3">
1632 <!-- ??? -->
1636 <domain varset="chip" name="CP_EVENT_WRITE7" width="32">
1637 <enum name="event_write_src">
1638 <!-- Write payload[0] -->
1639 <value value="0" name="EV_WRITE_USER_32B"/>
1640 <!-- Write payload[0] payload[1] -->
1641 <value value="1" name="EV_WRITE_USER_64B"/>
1642 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
1643 <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/>
1644 <value value="3" name="EV_WRITE_ALWAYSON"/>
1645 <!-- Write payload[1] regs starting at payload[0] offset -->
1646 <value value="4" name="EV_WRITE_REGS_CONTENT"/>
1649 <enum name="event_write_dst">
1650 <value value="0" name="EV_DST_RAM"/>
1651 <value value="1" name="EV_DST_ONCHIP"/>
1654 <reg32 offset="0" name="0">
1655 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1656 <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
1657 <!-- Write sample count at (iova + 16) -->
1658 <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
1659 <!-- *(iova + 8) = *(iova + 16) - *iova -->
1660 <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
1662 <!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
1663 <!-- Increment 16b BV counter. Valid only in BV pipe -->
1664 <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/>
1665 <!-- Increment 16b BR counter. Valid only in BR pipe -->
1666 <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/>
1667 <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/>
1668 <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/>
1670 <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
1671 <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
1672 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
1673 <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
1677 <reg32 offset="1" name="1">
1678 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1680 <reg32 offset="2" name="2">
1681 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1683 <reg32 offset="3" name="3">
1684 <bitfield name="PAYLOAD_0" low="0" high="31"/>
1686 <reg32 offset="4" name="4">
1687 <bitfield name="PAYLOAD_1" low="0" high="31"/>
1692 <reg32 offset="1" name="1">
1693 <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
1695 <reg32 offset="3" name="3">
1696 <bitfield name="PAYLOAD_0" low="0" high="31"/>
1698 <reg32 offset="4" name="4">
1699 <bitfield name="PAYLOAD_1" low="0" high="31"/>
1704 <domain name="CP_BLIT" width="32">
1705 <enum name="cp_blit_cmd">
1706 <value value="0" name="BLIT_OP_FILL"/>
1707 <value value="1" name="BLIT_OP_COPY"/>
1708 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1710 <reg32 offset="0" name="0">
1711 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1713 <reg32 offset="1" name="1">
1714 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1715 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1717 <reg32 offset="2" name="2">
1718 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1719 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1721 <reg32 offset="3" name="3">
1722 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1723 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1725 <reg32 offset="4" name="4">
1726 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1727 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1731 <domain name="CP_EXEC_CS" width="32">
1732 <reg32 offset="0" name="0">
1734 <reg32 offset="1" name="1">
1735 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1737 <reg32 offset="2" name="2">
1738 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1740 <reg32 offset="3" name="3">
1741 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1745 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1746 <reg32 offset="0" name="0">
1749 <reg32 offset="1" name="1">
1750 <bitfield name="ADDR" low="0" high="31"/>
1752 <reg32 offset="2" name="2">
1753 <!-- localsize is value minus one: -->
1754 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1755 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1756 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1759 <stripe varset="chip" variants="A5XX-">
1760 <reg32 offset="1" name="1">
1761 <bitfield name="ADDR_LO" low="0" high="31"/>
1763 <reg32 offset="2" name="2">
1764 <bitfield name="ADDR_HI" low="0" high="31"/>
1766 <reg32 offset="3" name="3">
1767 <!-- localsize is value minus one: -->
1768 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1769 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1770 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1775 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1777 <enum name="a6xx_marker">
1778 <value value="1" name="RM6_BYPASS"/>
1779 <value value="2" name="RM6_BINNING"/>
1780 <value value="4" name="RM6_GMEM"/>
1781 <value value="5" name="RM6_ENDVIS"/>
1782 <value value="6" name="RM6_RESOLVE"/>
1783 <value value="7" name="RM6_YIELD"/>
1784 <value value="8" name="RM6_COMPUTE"/>
1785 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1787 <!--
1790 -->
1791 <value value="0xd" name="RM6_IB1LIST_START"/>
1792 <value value="0xe" name="RM6_IB1LIST_END"/>
1793 <!-- IFPC - inter-frame power collapse -->
1794 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1795 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1797 <reg32 offset="0" name="0">
1798 <!--
1803 parsing works in the firmware, only b0-b3 are considered, but
1807 -->
1808 <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
1809 <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
1813 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1815 <enum name="pseudo_reg">
1816 <value value="0" name="SMMU_INFO"/>
1817 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1818 <value value="2" name="SECURE_SAVE_ADDR"/>
1819 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1820 <value value="4" name="COUNTER"/>
1822 <!--
1826 pseudo-regs instead, which do the right thing.
1835 -->
1836 <value value="8" name="DRAW_STRM_ADDRESS"/>
1837 <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
1838 <value value="10" name="PRIM_STRM_ADDRESS"/>
1839 <value value="11" name="UNK_STRM_ADDRESS"/>
1840 <value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
1842 <value value="16" name="BINDLESS_BASE_0_ADDR"/>
1843 <value value="17" name="BINDLESS_BASE_1_ADDR"/>
1844 <value value="18" name="BINDLESS_BASE_2_ADDR"/>
1845 <value value="19" name="BINDLESS_BASE_3_ADDR"/>
1846 <value value="20" name="BINDLESS_BASE_4_ADDR"/>
1847 <value value="21" name="BINDLESS_BASE_5_ADDR"/>
1848 <value value="22" name="BINDLESS_BASE_6_ADDR"/>
1851 <reg32 offset="0" name="0">
1852 <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/>
1854 <reg32 offset="1" name="1">
1855 <bitfield name="LO" low="0" high="31"/>
1857 <reg32 offset="2" name="2">
1858 <bitfield name="HI" low="0" high="31"/>
1863 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1878 <enum name="source_type">
1879 <value value="0" name="SOURCE_REG"/>
1880 <!-- Don't confuse with scratch registers, this is a separate memory
1881 written into by CP_MEM_TO_SCRATCH_MEM. -->
1882 <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
1884 <reg32 offset="0" name="0">
1885 <!-- the register to test -->
1886 <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
1887 …<bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATC…
1888 <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/>
1889 <!-- the bit to test -->
1890 <bitfield name="BIT" low="20" high="24" type="uint"/>
1891 <!-- skip implied CP_WAIT_FOR_ME -->
1892 <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
1893 <!-- the predicate bit to set (new in gen3+) -->
1894 <bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
1895 <!-- update the predicate reg directly (new in gen3+) -->
1896 <bitfield name="PRED_UPDATE" pos="31" type="boolean"/>
1899 <!--
1904 -->
1905 <reg32 offset="1" name="PRED_MASK" type="hex"/>
1906 <reg32 offset="2" name="PRED_VAL" type="hex"/>
1909 <!-- I *think* this existed at least as far back as a4xx -->
1910 <domain name="CP_COND_REG_EXEC" width="32">
1911 <enum name="compare_mode">
1912 <!-- use the predicate bit set by CP_REG_TEST -->
1913 <value value="1" name="PRED_TEST"/>
1914 <!-- compare two registers directly for equality -->
1915 <value value="2" name="REG_COMPARE"/>
1916 <!-- test if certain render modes are set via CP_SET_MARKER -->
1917 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
1918 <!-- compare REG0 for equality with immediate -->
1919 <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
1920 <!-- test which of BR/BV are enabled -->
1921 <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
1923 <reg32 offset="0" name="0" varset="compare_mode">
1924 <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
1926 <!-- the predicate bit to test (new in gen3+) -->
1927 <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
1928 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
1929 <!-- With REG_COMPARE instead of register read from ONCHIP memory -->
1930 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1932 <!--
1937 -->
1939 <!-- RM6_BINNING -->
1940 <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
1941 <!-- all others -->
1942 <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
1943 <!-- RM6_BYPASS -->
1944 <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
1946 <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
1947 <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/>
1948 <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/>
1950 <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
1954 <reg32 offset="1" name="1">
1955 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1960 <reg32 offset="1" name="1">
1961 <bitfield name="REG1" low="0" high="17" type="hex"/>
1962 <!-- Instead of register read from ONCHIP memory -->
1963 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1968 <reg32 offset="1" name="1">
1969 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1974 <reg32 offset="1" name="1">
1975 <bitfield name="IMM" low="0" high="31"/>
1980 <reg32 offset="1" name="1">
1981 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1985 <reg32 offset="2" name="2">
1986 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1990 <domain name="CP_COND_EXEC" width="32">
1996 <reg32 offset="0" name="0">
1997 <bitfield name="ADDR0_LO" low="0" high="31"/>
1999 <reg32 offset="1" name="1">
2000 <bitfield name="ADDR0_HI" low="0" high="31"/>
2002 <reg32 offset="2" name="2">
2003 <bitfield name="ADDR1_LO" low="0" high="31"/>
2005 <reg32 offset="3" name="3">
2006 <bitfield name="ADDR1_HI" low="0" high="31"/>
2008 <reg32 offset="4" name="4">
2009 <bitfield name="REF" low="0" high="31"/>
2011 <reg32 offset="5" name="5">
2012 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
2016 <domain name="CP_SET_CTXSWITCH_IB" width="32">
2023 <enum name="ctxswitch_ib">
2024 <value name="RESTORE_IB" value="0">
2027 <value name="YIELD_RESTORE_IB" value="1">
2038 <value name="SAVE_IB" value="2">
2045 <value name="RB_SAVE_IB" value="3">
2055 <reg32 offset="0" name="0">
2056 <bitfield name="ADDR_LO" low="0" high="31"/>
2058 <reg32 offset="1" name="1">
2059 <bitfield name="ADDR_HI" low="0" high="31"/>
2061 <reg32 offset="2" name="2">
2062 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
2063 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
2067 <domain name="CP_REG_WRITE" width="32">
2068 <enum name="reg_tracker">
2072 - VPC_CNTL_0
2073 - HLSQ_CONTROL_1_REG
2074 - HLSQ_UNKNOWN_B980
2076 <value name="TRACK_CNTL_REG" value="0x1"/>
2080 - There is a write that disables binning
2081 - There was a draw with binning left enabled, but in
2085 <value name="TRACK_RENDER_CNTL" value="0x2"/>
2092 <value name="UNK_EVENT_WRITE" value="0x4"/>
2097 - GRAS_LRZ_CNTL::GREATER has changed
2098 - GRAS_LRZ_CNTL::DIR has changed, the old value is not
2100 - GRAS_LRZ_DEPTH_VIEW has changed
2105 <value name="TRACK_LRZ" value="0x8"/>
2107 <reg32 offset="0" name="0">
2108 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
2110 <reg32 offset="1" name="1"/>
2111 <reg32 offset="2" name="2"/>
2114 <domain name="CP_SMMU_TABLE_UPDATE" width="32">
2120 <reg32 offset="0" name="0">
2121 <bitfield name="TTBR0_LO" low="0" high="31"/>
2123 <reg32 offset="1" name="1">
2124 <bitfield name="TTBR0_HI" low="0" high="15"/>
2125 <bitfield name="ASID" low="16" high="31"/>
2127 <reg32 offset="2" name="2">
2129 <bitfield name="CONTEXTIDR" low="0" high="31"/>
2131 <reg32 offset="3" name="3">
2132 <bitfield name="CONTEXTBANK" low="0" high="31"/>
2136 <domain name="CP_START_BIN" width="32">
2137 <reg32 offset="0" name="BIN_COUNT" type="uint"/>
2138 <reg64 offset="1" name="PREFIX_ADDR" type="address"/>
2139 <reg32 offset="3" name="PREFIX_DWORDS">
2147 <reg32 offset="4" name="BODY_DWORDS">
2152 <domain name="CP_WAIT_TIMESTAMP" width="32">
2153 <enum name="ts_wait_value_src">
2154 <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
2155 <value value="0" name="TS_WAIT_GE_32B"/>
2156 <!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
2157 <value value="1" name="TS_WAIT_GE_64B"/>
2158 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
2159 <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
2162 <enum name="ts_wait_type">
2163 <value value="0" name="TS_WAIT_RAM"/>
2164 <value value="1" name="TS_WAIT_ONCHIP"/>
2167 <reg32 offset="0" name="0">
2168 <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
2169 <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/>
2173 <reg64 offset="1" name="ADDR" type="address"/>
2177 <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
2180 <reg32 offset="3" name="SRC_0"/>
2181 <reg32 offset="4" name="SRC_1"/>
2184 <domain name="CP_BV_BR_COUNT_OPS" width="32">
2185 <enum name="pipe_count_op">
2186 <value name="PIPE_CLEAR_BV_BR" value="0x1"/>
2187 <value name="PIPE_SET_BR_OFFSET" value="0x2"/>
2188 <!-- Wait until for BV_counter > BR_counter -->
2189 <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/>
2190 <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter -->
2191 <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/>
2193 <reg32 offset="0" name="0">
2194 <bitfield name="OP" low="0" high="3" type="pipe_count_op"/>
2196 <reg32 offset="1" name="1">
2197 <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/>
2201 <domain name="CP_MODIFY_TIMESTAMP" width="32">
2202 <enum name="timestamp_op">
2203 <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/>
2204 <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/>
2205 <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/>
2207 <reg32 offset="0" name="0">
2208 <bitfield name="ADD" low="0" high="7" type="uint"/>
2209 <bitfield name="OP" low="28" high="31" type="timestamp_op"/>
2213 <domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
2219 <reg32 offset="0" name="0">
2220 <bitfield name="CNT" low="0" high="5" type="uint"/>
2222 <reg32 offset="1" name="1">
2224 <bitfield name="OFFSET" low="0" high="5" type="uint"/>
2226 <reg32 offset="2" name="2">
2227 <bitfield name="SRC" low="0" high="31"/>
2229 <reg32 offset="3" name="3">
2230 <bitfield name="SRC_HI" low="0" high="31"/>
2234 <domain name="CP_THREAD_CONTROL" width="32">
2235 <enum name="cp_thread">
2236 <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
2237 <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
2238 <value name="CP_SET_THREAD_BOTH" value="3"/>
2240 <reg32 offset="0" name="0">
2241 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
2242 <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/>
2243 <bitfield pos="31" name="SYNC_THREADS" type="boolean"/>
2247 <domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32">
2248 <reg64 offset="0" name="IB_BASE"/>
2249 <reg32 offset="2" name="2">
2250 <!-- STRIDE * COUNT -->
2251 <bitfield name="IB_SIZE" low="0" high="11"/>
2252 <bitfield name="STRIDE" low="20" high="31"/>
2254 <reg32 offset="3" name="3">
2255 <bitfield name="COUNT" low="0" high="31"/>
2259 <domain name="CP_RESET_CONTEXT_STATE" width="32">
2260 <reg32 offset="0" name="0">
2261 <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/>
2262 <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/>
2263 <bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/>