Lines Matching +full:low +full:-
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
19 <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
28 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
29 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
30 <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
31 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
45 <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
47 <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
48 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
50 <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
52 <!-- a5xx events -->
53 <value name="WT_DONE_TS" value="8" variants="A5XX-"/>
54 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
55 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
56 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
57 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
58 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
59 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
60 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
61 <value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
67 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
73 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
91 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
98 <value name="BLIT" value="30" variants="A5XX-"/>
102 fast-clear buffer or LRZ direction.
111 <value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
113 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
114 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
115 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
117 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
118 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
119 <value name="UNK_2C" value="44" variants="A5XX-"/>
120 <value name="UNK_2D" value="45" variants="A5XX-"/>
122 <!-- a6xx events -->
128 <value name="LABEL" value="63" variants="A6XX-"/>
130 <!-- note, some of these are the same as a6xx, just named differently -->
145 <!-- TODO: deal with name conflicts with other gens -->
152 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
159 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
237 <!--
243 disambiguate the packet-id's that were re-used for different
245 -->
247 <doc>initialize CP's micro-engine</doc>
249 <doc>skip N 32-bit words to get to the next packet</doc>
253 type to determine whether to pre-fetch the IB
263 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
276 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
278 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
280 <!--
283 -->
284 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
288 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
289 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
292 <doc>write N 32-bit words to memory</doc>
299 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
300 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
302 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
303 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
318 …DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unu…
320 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
322 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
324 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
325 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
329 <doc>load sequencer instruction memory (pointer-based)</doc>
338 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
339 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
340 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
341 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
342 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
350 <!-- For a20x -->
351 <!-- TODO handle variants..
357 -->
359 <!-- for a22x -->
361 sets draw initiator flags register in PFP, gets bitwise-ORed into
370 <!-- for a3xx -->
373 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
378 <doc>Load a buffer with pre-fetch enabled</doc>
389 <doc>Record the real-time when this packet is processed by PFP</doc>
392 <!-- Used to switch GPU between secure and non-secure modes -->
398 <!-- for a4xx -->
408 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
410 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
411 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
412 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
442 Write to register with address that does not fit into type-0 pkt
461 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/>
468 <!-- switches SMMU pagetable, used on a5xx+ only -->
469 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
470 <!-- for a6xx -->
472 <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
474 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/>
475 <!--
478 -->
479 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/>
480 <!-- A5XX Enable yield in RB only -->
488 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
489 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
490 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
491 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
492 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/>
493 <!-- Enable/Disable/Defer A5x global preemption model -->
495 <!-- Enable/Disable A5x local preemption model -->
497 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
498 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/>
499 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
502 <!-- check if this works on earlier.. -->
503 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
510 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
512 <!-- Test specified bit in specified register and set predicate -->
513 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
515 <!--
521 -->
522 <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
524 <!--
537 -->
538 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
539 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
540 <!--
545 -->
546 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
548 <!-- internal packets: -->
558 <!-- internal jumptable entries on a6xx+, possibly a5xx: -->
560 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
561 <value name="PKT4" value="0x04" variants="A5XX-"/>
562 <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
563 <value name="IN_IB_END" value="0x0a" variants="A6XX-"/>
564 <!-- handles IFPC save/restore -->
565 <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/>
566 <!-- preemption/context-swtich routine -->
567 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
569 <!-- TODO do these exist on A5xx? -->
571 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
572 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
575 <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
576 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/>
577 <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
578 <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
584 <!-- Note, kgsl calls this CP_SET_AMBLE: -->
585 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
587 <!--
605 -->
611 used to loop over bins. There is a fixed-size per-iteration
612 prefix, used to set per-bin state, and then the following IB1
620 <value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
621 <value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
623 <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
626 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
627 <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
628 …e name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
629 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
630 …<!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for G…
631 <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
633 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
635 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/>
636 <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
637 <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
643 <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
646 Executes an array of fixed-size command buffers where each
648 non-visible draw calls.
650 <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
652 <doc>Reset various on-chip state used for synchronization</doc>
653 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
686 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
687 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
688 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
689 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
692 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
693 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
700 <!--
701 unknown: 0x7 and 0xf <- seen in compute shader
708 16 -> vert
709 36 -> tcs
710 56 -> tes
711 76 -> geom
712 96 -> frag
733 -->
735 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
736 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
746 <!--
752 -->
766 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
767 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
768 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
769 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
772 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
773 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
775 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
776 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
780 <!-- looks basically same CP_LOAD_STATE4 -->
785 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
786 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
807 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
819 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
820 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
821 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
822 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
823 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
826 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
829 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
835 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
836 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
837 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
842 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
845 <!-- changed on a4xx: -->
859 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
860 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
861 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
862 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
863 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
864 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
871 <bitfield name="VIZ_QUERY" low="0" high="31"/>
875 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
878 <bitfield name="INDX_BASE" low="0" high="31"/>
881 <bitfield name="INDX_SIZE" low="0" high="31"/>
887 <bitfield name="VIZ_QUERY" low="0" high="31"/>
891 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
893 <!-- followed by NUM_INDICES indices.. -->
899 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
902 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
905 <bitfield name="FIRST_INDX" low="0" high="31"/>
908 <stripe varset="chip" variants="A5XX-">
910 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
913 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
917 <!-- max # of elements in index buffer -->
918 <bitfield name="MAX_INDICES" low="0" high="31"/>
923 <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
927 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
931 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
935 <bitfield name="INDIRECT" low="0" high="31"/>
938 <stripe varset="chip" variants="A5XX-">
940 <bitfield name="INDIRECT_LO" low="0" high="31"/>
943 <bitfield name="INDIRECT_HI" low="0" high="31"/>
949 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
953 <bitfield name="INDX_BASE" low="0" high="31"/>
956 <!-- max # of bytes in index buffer -->
957 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
960 <bitfield name="INDIRECT" low="0" high="31"/>
963 <stripe varset="chip" variants="A5XX-">
965 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
968 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
972 <!-- max # of elements in index buffer -->
973 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
976 <bitfield name="INDIRECT_LO" low="0" high="31"/>
979 <bitfield name="INDIRECT_HI" low="0" high="31"/>
985 <domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
994 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
996 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
1000 <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
1030 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
1034 <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/>
1037 <bitfield name="STRIDE" low="0" high="31" type="uint"/>
1055 <!--
1056 Sources 1-4 seem to be about combining reading
1058 a DX11-specific optimization (since in DX11 you can only
1060 -->
1063 Read a 64-bit value at the given address and
1073 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
1079 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
1082 <bitfield name="COUNT" low="0" high="15" type="uint"/>
1087 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
1088 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
1089 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
1090 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
1093 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
1095 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1096 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
1105 <bitfield name="X1" low="0" high="15" type="uint"/>
1106 <bitfield name="Y1" low="16" high="31" type="uint"/>
1109 <bitfield name="X2" low="0" high="15" type="uint"/>
1110 <bitfield name="Y2" low="16" high="31" type="uint"/>
1116 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
1117 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
1120 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
1121 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
1127 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1128 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1129 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1130 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
1132 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1134 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
1137 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
1139 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1141 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
1144 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
1146 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
1148 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
1151 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
1153 <!--
1155 -->
1168 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1169 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1170 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1171 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
1173 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1175 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
1177 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1179 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
1181 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
1183 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
1201 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
1202 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
1208 <bitfield name="SRC0" low="0" high="31" type="uint"/>
1211 <bitfield name="SRC1" low="0" high="31" type="uint"/>
1217 <bitfield name="REG" low="0" high="17" type="hex"/>
1218 <!-- number of registers/dwords copied is max(CNT, 1). -->
1219 <bitfield name="CNT" low="18" high="29" type="uint"/>
1224 <bitfield name="DEST" low="0" high="31"/>
1226 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1227 <bitfield name="DEST_HI" low="0" high="31"/>
1238 <bitfield name="REG" low="0" high="17" type="hex"/>
1239 <!-- number of registers/dwords copied is max(CNT, 1). -->
1240 <bitfield name="CNT" low="18" high="29" type="uint"/>
1245 <bitfield name="DEST" low="0" high="31"/>
1247 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1248 <bitfield name="DEST_HI" low="0" high="31"/>
1251 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
1254 <!-- followed by an optional identical OFFSET1 dword -->
1263 <bitfield name="REG" low="0" high="17" type="hex"/>
1264 <!-- number of registers/dwords copied is max(CNT, 1). -->
1265 <bitfield name="CNT" low="18" high="29" type="uint"/>
1270 <bitfield name="DEST" low="0" high="31"/>
1272 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1273 <bitfield name="DEST_HI" low="0" high="31"/>
1276 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1279 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1285 <bitfield name="REG" low="0" high="17" type="hex"/>
1286 <!-- number of registers/dwords copied is max(CNT, 1). -->
1287 <bitfield name="CNT" low="19" high="29" type="uint"/>
1288 <!-- shift each DWORD left by 2 while copying -->
1290 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1294 <bitfield name="SRC" low="0" high="31"/>
1296 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1297 <bitfield name="SRC_HI" low="0" high="31"/>
1303 <!--
1304 not sure how many src operands we have, but the low
1306 -->
1311 <!-- if set treat src/dst as 64bit values -->
1313 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1315 <!-- some other kind of wait -->
1318 <!--
1322 to do things like 'result += end - start' (which turns
1325 -->
1330 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1333 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1336 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1339 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1342 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1348 <bitfield name="REG" low="0" high="17" type="hex"/>
1349 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1350 <!-- number of registers/dwords copied is CNT + 1. -->
1351 <bitfield name="CNT" low="24" high="26" type="uint"/>
1357 <bitfield name="REG" low="0" high="17" type="hex"/>
1358 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1360 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1361 <!-- number of registers/dwords copied is CNT + 1. -->
1362 <bitfield name="CNT" low="24" high="26" type="uint"/>
1368 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1370 <!-- followed by one or more DWORDs to write to scratch registers -->
1375 <bitfield name="ADDR_LO" low="0" high="31"/>
1378 <bitfield name="ADDR_HI" low="0" high="31"/>
1380 <!-- followed by the DWORDs to write -->
1395 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1400 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1403 <bitfield name="REF" low="0" high="31"/>
1406 <bitfield name="MASK" low="0" high="31"/>
1409 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1412 <bitfield name="WRITE_DATA" low="0" high="31"/>
1420 <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
1425 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1427 <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
1428 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1432 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1435 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1438 <bitfield name="REF" low="0" high="31"/>
1441 <bitfield name="MASK" low="0" high="31"/>
1444 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1447 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1450 <bitfield name="WRITE_DATA" low="0" high="31"/>
1460 <!-- Reserved for flags, presumably? Unused in FW -->
1461 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1464 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1467 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1470 <bitfield name="REF" low="0" high="31"/>
1477 but waits until the comparison is true instead. It busy-loops in
1481 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1483 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1487 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1490 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1493 <bitfield name="REF" low="0" high="31"/>
1496 <bitfield name="MASK" low="0" high="31"/>
1499 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1508 <bitfield name="REG0" low="0" high="17" type="hex"/>
1511 <bitfield name="REG1" low="0" high="17" type="hex"/>
1514 <bitfield name="REF" low="0" high="31" type="uint"/>
1521 <bitfield name="X" low="0" high="31"/>
1524 <bitfield name="Y" low="0" high="31"/>
1527 <bitfield name="Z" low="0" high="31"/>
1537 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1539 <!-- 8 set before going back to BYPASS exiting 2D -->
1543 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1544 <!--
1548 -->
1550 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1552 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1555 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1558 <!--
1561 -->
1566 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1568 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1571 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1574 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1578 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1580 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1582 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1585 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1590 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1592 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1595 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1598 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1607 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1610 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1616 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1617 <!-- when set, write back timestamp instead of value from packet: -->
1621 <!--
1624 -->
1626 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1629 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1632 <!-- ??? -->
1638 <!-- Write payload[0] -->
1640 <!-- Write payload[0] payload[1] -->
1642 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
1645 <!-- Write payload[1] regs starting at payload[0] offset -->
1655 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1657 <!-- Write sample count at (iova + 16) -->
1659 <!-- *(iova + 8) = *(iova + 16) - *iova -->
1662 <!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
1663 <!-- Increment 16b BV counter. Valid only in BV pipe -->
1665 <!-- Increment 16b BR counter. Valid only in BR pipe -->
1670 <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
1672 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
1678 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1681 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1684 <bitfield name="PAYLOAD_0" low="0" high="31"/>
1687 <bitfield name="PAYLOAD_1" low="0" high="31"/>
1693 <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
1696 <bitfield name="PAYLOAD_0" low="0" high="31"/>
1699 <bitfield name="PAYLOAD_1" low="0" high="31"/>
1708 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1711 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1714 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1715 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1718 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1719 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1722 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1723 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1726 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1727 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1735 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1738 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1741 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1745 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1750 <bitfield name="ADDR" low="0" high="31"/>
1753 <!-- localsize is value minus one: -->
1754 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1755 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1756 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1759 <stripe varset="chip" variants="A5XX-">
1761 <bitfield name="ADDR_LO" low="0" high="31"/>
1764 <bitfield name="ADDR_HI" low="0" high="31"/>
1767 <!-- localsize is value minus one: -->
1768 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1769 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1770 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1775 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1785 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1787 <!--
1790 -->
1793 <!-- IFPC - inter-frame power collapse -->
1798 <!--
1803 parsing works in the firmware, only b0-b3 are considered, but
1804 if b8 is set, the low bits are interpreted differently. To
1807 -->
1808 <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
1809 <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
1813 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1822 <!--
1826 pseudo-regs instead, which do the right thing.
1835 -->
1852 <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/>
1855 <bitfield name="LO" low="0" high="31"/>
1858 <bitfield name="HI" low="0" high="31"/>
1863 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1880 <!-- Don't confuse with scratch registers, this is a separate memory
1881 written into by CP_MEM_TO_SCRATCH_MEM. -->
1882 <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
1885 <!-- the register to test -->
1886 <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
1887 …<bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATC…
1889 <!-- the bit to test -->
1890 <bitfield name="BIT" low="20" high="24" type="uint"/>
1891 <!-- skip implied CP_WAIT_FOR_ME -->
1893 <!-- the predicate bit to set (new in gen3+) -->
1894 <bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
1895 <!-- update the predicate reg directly (new in gen3+) -->
1899 <!--
1904 -->
1909 <!-- I *think* this existed at least as far back as a4xx -->
1912 <!-- use the predicate bit set by CP_REG_TEST -->
1914 <!-- compare two registers directly for equality -->
1916 <!-- test if certain render modes are set via CP_SET_MARKER -->
1917 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
1918 <!-- compare REG0 for equality with immediate -->
1919 <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
1920 <!-- test which of BR/BV are enabled -->
1921 <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
1924 <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
1926 <!-- the predicate bit to test (new in gen3+) -->
1927 <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
1928 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
1929 <!-- With REG_COMPARE instead of register read from ONCHIP memory -->
1930 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1932 <!--
1937 -->
1939 <!-- RM6_BINNING -->
1941 <!-- all others -->
1943 <!-- RM6_BYPASS -->
1950 <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
1955 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1961 <bitfield name="REG1" low="0" high="17" type="hex"/>
1962 <!-- Instead of register read from ONCHIP memory -->
1963 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1969 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1975 <bitfield name="IMM" low="0" high="31"/>
1981 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1986 <bitfield name="DWORDS" low="0" high="23" type="uint"/>
1997 <bitfield name="ADDR0_LO" low="0" high="31"/>
2000 <bitfield name="ADDR0_HI" low="0" high="31"/>
2003 <bitfield name="ADDR1_LO" low="0" high="31"/>
2006 <bitfield name="ADDR1_HI" low="0" high="31"/>
2009 <bitfield name="REF" low="0" high="31"/>
2012 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
2056 <bitfield name="ADDR_LO" low="0" high="31"/>
2059 <bitfield name="ADDR_HI" low="0" high="31"/>
2062 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
2063 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
2072 - VPC_CNTL_0
2073 - HLSQ_CONTROL_1_REG
2074 - HLSQ_UNKNOWN_B980
2080 - There is a write that disables binning
2081 - There was a draw with binning left enabled, but in
2087 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
2097 - GRAS_LRZ_CNTL::GREATER has changed
2098 - GRAS_LRZ_CNTL::DIR has changed, the old value is not
2100 - GRAS_LRZ_DEPTH_VIEW has changed
2108 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
2121 <bitfield name="TTBR0_LO" low="0" high="31"/>
2124 <bitfield name="TTBR0_HI" low="0" high="15"/>
2125 <bitfield name="ASID" low="16" high="31"/>
2129 <bitfield name="CONTEXTIDR" low="0" high="31"/>
2132 <bitfield name="CONTEXTBANK" low="0" high="31"/>
2154 <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
2156 <!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
2158 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
2168 <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
2177 <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
2188 <!-- Wait until for BV_counter > BR_counter -->
2190 <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter -->
2194 <bitfield name="OP" low="0" high="3" type="pipe_count_op"/>
2197 <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/>
2208 <bitfield name="ADD" low="0" high="7" type="uint"/>
2209 <bitfield name="OP" low="28" high="31" type="timestamp_op"/>
2220 <bitfield name="CNT" low="0" high="5" type="uint"/>
2224 <bitfield name="OFFSET" low="0" high="5" type="uint"/>
2227 <bitfield name="SRC" low="0" high="31"/>
2230 <bitfield name="SRC_HI" low="0" high="31"/>
2236 <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
2237 <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
2241 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
2250 <!-- STRIDE * COUNT -->
2251 <bitfield name="IB_SIZE" low="0" high="11"/>
2252 <bitfield name="STRIDE" low="20" high="31"/>
2255 <bitfield name="COUNT" low="0" high="31"/>