Lines Matching +full:name +full:-
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
7 <enum name="chip" bare="yes">
8 <value name="A2XX" value="2"/>
9 <value name="A3XX" value="3"/>
10 <value name="A4XX" value="4"/>
11 <value name="A5XX" value="5"/>
12 <value name="A6XX" value="6"/>
13 <value name="A7XX" value="7"/>
16 <enum name="adreno_pa_su_sc_draw">
17 <value name="PC_DRAW_POINTS" value="0"/>
18 <value name="PC_DRAW_LINES" value="1"/>
19 <value name="PC_DRAW_TRIANGLES" value="2"/>
22 <enum name="adreno_compare_func">
23 <value name="FUNC_NEVER" value="0"/>
24 <value name="FUNC_LESS" value="1"/>
25 <value name="FUNC_EQUAL" value="2"/>
26 <value name="FUNC_LEQUAL" value="3"/>
27 <value name="FUNC_GREATER" value="4"/>
28 <value name="FUNC_NOTEQUAL" value="5"/>
29 <value name="FUNC_GEQUAL" value="6"/>
30 <value name="FUNC_ALWAYS" value="7"/>
33 <enum name="adreno_stencil_op">
34 <value name="STENCIL_KEEP" value="0"/>
35 <value name="STENCIL_ZERO" value="1"/>
36 <value name="STENCIL_REPLACE" value="2"/>
37 <value name="STENCIL_INCR_CLAMP" value="3"/>
38 <value name="STENCIL_DECR_CLAMP" value="4"/>
39 <value name="STENCIL_INVERT" value="5"/>
40 <value name="STENCIL_INCR_WRAP" value="6"/>
41 <value name="STENCIL_DECR_WRAP" value="7"/>
44 <enum name="adreno_rb_blend_factor">
45 <value name="FACTOR_ZERO" value="0"/>
46 <value name="FACTOR_ONE" value="1"/>
47 <value name="FACTOR_SRC_COLOR" value="4"/>
48 <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
49 <value name="FACTOR_SRC_ALPHA" value="6"/>
50 <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
51 <value name="FACTOR_DST_COLOR" value="8"/>
52 <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
53 <value name="FACTOR_DST_ALPHA" value="10"/>
54 <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
55 <value name="FACTOR_CONSTANT_COLOR" value="12"/>
56 <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
57 <value name="FACTOR_CONSTANT_ALPHA" value="14"/>
58 <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
59 <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
60 <value name="FACTOR_SRC1_COLOR" value="20"/>
61 <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
62 <value name="FACTOR_SRC1_ALPHA" value="22"/>
63 <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
66 <bitset name="adreno_rb_stencilrefmask" inline="yes">
67 <bitfield name="STENCILREF" low="0" high="7" type="hex"/>
68 <bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
69 <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
72 <enum name="adreno_rb_surface_endian">
73 <value name="ENDIAN_NONE" value="0"/>
74 <value name="ENDIAN_8IN16" value="1"/>
75 <value name="ENDIAN_8IN32" value="2"/>
76 <value name="ENDIAN_16IN32" value="3"/>
77 <value name="ENDIAN_8IN64" value="4"/>
78 <value name="ENDIAN_8IN128" value="5"/>
81 <enum name="adreno_rb_dither_mode">
82 <value name="DITHER_DISABLE" value="0"/>
83 <value name="DITHER_ALWAYS" value="1"/>
84 <value name="DITHER_IF_ALPHA_OFF" value="2"/>
87 <enum name="adreno_rb_depth_format">
88 <value name="DEPTHX_16" value="0"/>
89 <value name="DEPTHX_24_8" value="1"/>
90 <value name="DEPTHX_32" value="2"/>
93 <enum name="adreno_rb_copy_control_mode">
94 <value name="RB_COPY_RESOLVE" value="1"/>
95 <value name="RB_COPY_CLEAR" value="2"/>
96 …<value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another …
99 <bitset name="adreno_reg_xy" inline="yes">
100 <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
101 <bitfield name="X" low="0" high="14" type="uint"/>
102 <bitfield name="Y" low="16" high="30" type="uint"/>
105 <bitset name="adreno_cp_protect" inline="yes">
106 <bitfield name="BASE_ADDR" low="0" high="16"/>
107 <bitfield name="MASK_LEN" low="24" high="28"/>
108 <bitfield name="TRAP_WRITE" pos="29"/>
109 <bitfield name="TRAP_READ" pos="30"/>
112 <domain name="AXXX" width="32">
115 <reg32 offset="0x01c0" name="CP_RB_BASE"/>
116 <reg32 offset="0x01c1" name="CP_RB_CNTL">
117 <bitfield name="BUFSZ" low="0" high="5"/>
118 <bitfield name="BLKSZ" low="8" high="13"/>
119 <bitfield name="BUF_SWAP" low="16" high="17"/>
120 <bitfield name="POLL_EN" pos="20" type="boolean"/>
121 <bitfield name="NO_UPDATE" pos="27" type="boolean"/>
122 <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
124 <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
125 <bitfield name="SWAP" low="0" high="1" type="uint"/>
126 <bitfield name="ADDR" low="2" high="31" shr="2"/>
128 <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
129 <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
130 <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
131 <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
132 <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
133 <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
134 <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
135 <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
136 <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
138 <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
139 <bitfield name="MEQ_END" low="16" high="20" type="uint"/>
140 <bitfield name="ROQ_END" low="24" high="28" type="uint"/>
142 <reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
143 <bitfield name="RING" low="0" high="6" type="uint"/>
144 <bitfield name="IB1" low="8" high="14" type="uint"/>
145 <bitfield name="IB2" low="16" high="22" type="uint"/>
147 <reg32 offset="0x01d8" name="CP_STQ_AVAIL">
148 <bitfield name="ST" low="0" high="6" type="uint"/>
150 <reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
151 <bitfield name="MEQ" low="0" high="4" type="uint"/>
153 <reg32 offset="0x01dc" name="SCRATCH_UMSK">
154 <bitfield name="UMSK" low="0" high="7" type="uint"/>
155 <bitfield name="SWAP" low="16" high="17" type="uint"/>
157 <reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
158 <reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
160 <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
161 <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
162 <reg32 offset="0x01f2" name="CP_INT_CNTL">
163 <bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
164 <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
165 <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
166 <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
167 <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
168 <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
169 <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
170 <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
171 <bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
173 <reg32 offset="0x01f3" name="CP_INT_STATUS"/>
174 <reg32 offset="0x01f4" name="CP_INT_ACK"/>
175 <reg32 offset="0x01f6" name="CP_ME_CNTL">
176 <bitfield name="BUSY" pos="29" type="boolean"/>
177 <bitfield name="HALT" pos="28" type="boolean"/>
179 <reg32 offset="0x01f7" name="CP_ME_STATUS"/>
180 <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
181 <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
182 <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
183 <reg32 offset="0x01fc" name="CP_DEBUG">
184 <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
185 <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
186 <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
187 <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
188 <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
189 <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
190 <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
191 <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
193 <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
194 <bitfield name="RPTR" low="0" high="6" type="uint"/>
195 <bitfield name="WPTR" low="16" high="22" type="uint"/>
197 <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
198 <bitfield name="RPTR" low="0" high="6" type="uint"/>
199 <bitfield name="WPTR" low="16" high="22" type="uint"/>
201 <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
202 <bitfield name="RPTR" low="0" high="6" type="uint"/>
203 <bitfield name="WPTR" low="16" high="22" type="uint"/>
206 <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
207 <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
208 <reg32 offset="0x044d" name="CP_ST_BASE"/>
209 <reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
210 <reg32 offset="0x044f" name="CP_MEQ_STAT"/>
211 <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
212 <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
213 <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
214 <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
215 <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
216 <reg32 offset="0x0458" name="CP_IB1_BASE"/>
217 <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
218 <reg32 offset="0x045a" name="CP_IB2_BASE"/>
219 <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
220 <reg32 offset="0x047f" name="CP_STAT">
221 <bitfield pos="31" name="CP_BUSY"/>
222 <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
223 <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
224 <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
225 <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
226 <bitfield pos="26" name="ME_BUSY"/>
227 <bitfield pos="25" name="MIU_WR_C_BUSY"/>
228 <bitfield pos="23" name="CP_3D_BUSY"/>
229 <bitfield pos="22" name="CP_NRT_BUSY"/>
230 <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
231 <bitfield pos="20" name="RCIU_ME_BUSY"/>
232 <bitfield pos="19" name="RCIU_PFP_BUSY"/>
233 <bitfield pos="18" name="MEQ_RING_BUSY"/>
234 <bitfield pos="17" name="PFP_BUSY"/>
235 <bitfield pos="16" name="ST_QUEUE_BUSY"/>
236 <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
237 <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
238 <bitfield pos="11" name="RING_QUEUE_BUSY"/>
239 <bitfield pos="10" name="CSF_BUSY"/>
240 <bitfield pos="9" name="CSF_ST_BUSY"/>
241 <bitfield pos="8" name="EVENT_BUSY"/>
242 <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/>
243 <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/>
244 <bitfield pos="5" name="CSF_RING_BUSY"/>
245 <bitfield pos="4" name="RCIU_BUSY"/>
246 <bitfield pos="3" name="RBIU_BUSY"/>
247 <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/>
248 <bitfield pos="1" name="MIU_RD_REQ_BUSY"/>
249 <bitfield pos="0" name="MIU_WR_BUSY"/>
251 <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
252 <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
253 <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
254 <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
255 <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
256 <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
257 <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
258 <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
260 <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
261 <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
262 <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
263 <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
264 <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
265 <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
266 <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
267 <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
268 <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
269 <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
270 <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
271 <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
272 <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
273 <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
274 <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
275 <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
276 <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
277 <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
281 <!--
283 -->
285 <enum name="a3xx_rop_code">
286 <value name="ROP_CLEAR" value="0"/>
287 <value name="ROP_NOR" value="1"/>
288 <value name="ROP_AND_INVERTED" value="2"/>
289 <value name="ROP_COPY_INVERTED" value="3"/>
290 <value name="ROP_AND_REVERSE" value="4"/>
291 <value name="ROP_INVERT" value="5"/>
292 <value name="ROP_XOR" value="6"/>
293 <value name="ROP_NAND" value="7"/>
294 <value name="ROP_AND" value="8"/>
295 <value name="ROP_EQUIV" value="9"/>
296 <value name="ROP_NOOP" value="10"/>
297 <value name="ROP_OR_INVERTED" value="11"/>
298 <value name="ROP_COPY" value="12"/>
299 <value name="ROP_OR_REVERSE" value="13"/>
300 <value name="ROP_OR" value="14"/>
301 <value name="ROP_SET" value="15"/>
304 <enum name="a3xx_render_mode">
305 <value name="RB_RENDERING_PASS" value="0"/>
306 <value name="RB_TILING_PASS" value="1"/>
307 <value name="RB_RESOLVE_PASS" value="2"/>
308 <value name="RB_COMPUTE_PASS" value="3"/>
311 <enum name="a3xx_msaa_samples">
312 <value name="MSAA_ONE" value="0"/>
313 <value name="MSAA_TWO" value="1"/>
314 <value name="MSAA_FOUR" value="2"/>
315 <value name="MSAA_EIGHT" value="3"/>
318 <enum name="a3xx_threadmode">
319 <value value="0" name="MULTI"/>
320 <value value="1" name="SINGLE"/>
323 <enum name="a3xx_instrbuffermode">
324 <!--
328 '0' the other gets size 256-others_size. So I think that:
334 -->
335 <value value="0" name="CACHE"/>
336 <value value="1" name="BUFFER"/>
339 <enum name="a3xx_threadsize">
340 <value value="0" name="TWO_QUADS"/>
341 <value value="1" name="FOUR_QUADS"/>
344 <enum name="a3xx_color_swap">
345 <value name="WZYX" value="0"/>
346 <value name="WXYZ" value="1"/>
347 <value name="ZYXW" value="2"/>
348 <value name="XYZW" value="3"/>
351 <enum name="a3xx_rb_blend_opcode">
352 <value name="BLEND_DST_PLUS_SRC" value="0"/>
353 <value name="BLEND_SRC_MINUS_DST" value="1"/>
354 <value name="BLEND_DST_MINUS_SRC" value="2"/>
355 <value name="BLEND_MIN_DST_SRC" value="3"/>
356 <value name="BLEND_MAX_DST_SRC" value="4"/>
359 <enum name="a4xx_tess_spacing">
360 <value name="EQUAL_SPACING" value="0"/>
361 <value name="ODD_SPACING" value="2"/>
362 <value name="EVEN_SPACING" value="3"/>
366 <enum name="a5xx_address_mode">
367 <value name="ADDR_32B" value="0"/>
368 <value name="ADDR_64B" value="1"/>
375 <enum name="a5xx_line_mode">
376 <value value="0x0" name="BRESENHAM"/>
377 <value value="0x1" name="RECTANGULAR"/>
386 <enum name="a6xx_tex_prefetch_cmd">
388 <value value="0x0" name="TEX_PREFETCH_UNK0"/>
389 <value value="0x1" name="TEX_PREFETCH_SAM"/>
390 <value value="0x2" name="TEX_PREFETCH_GATHER4R"/>
391 <value value="0x3" name="TEX_PREFETCH_GATHER4G"/>
392 <value value="0x4" name="TEX_PREFETCH_GATHER4B"/>
393 <value value="0x5" name="TEX_PREFETCH_GATHER4A"/>
395 <value value="0x6" name="TEX_PREFETCH_UNK6"/>
397 <value value="0x7" name="TEX_PREFETCH_UNK7"/>