Lines Matching +full:swap +full:- +full:xy
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
9 <!--
12 - "cmd" - the register is used outside of renderpass and blits,
14 - "rp_blit" - the register is used inside renderpass or blits
21 -->
23 <!-- these might be same as a5xx -->
39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
121 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
122 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
123 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
125 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
129 <!-- Note: tiling/UBWC for these may be different from equivalent formats
131 -->
180 <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
183 <!-- Not a hw enum, used internally in driver -->
188 <!-- probably same as a5xx -->
1121 <!--
1137 -->
1150 <doc>Allow early z-test and early-lrz (if applicable)</doc>
1152 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
1155 A special mode that allows early-lrz test but disables
1156 early-z test. Which might sound a bit funny, since
1157 lrz-test happens before z-test. But as long as a couple
1158 conditions are maintained this allows using lrz-test in
1161 1) Disable lrz-write in cases where it is uncertain during
1163 shader has-kill, writes-z, or alpha/stencil test is
1164 enabled. (For correctness, lrz-write must be disabled
1166 z-prepass works.
1168 2) Disable lrz-write and test if a depth-test direction
1173 lrz-test. But geometry which may be (or contributes to
1174 blend) will pass the lrz-test.
1176 This allows us to keep early-lrz-test in cases where the frag
1177 shader does not write-z (ie. we know the z-value before FS)
1178 and does not have side-effects (image/ssbo writes, etc), but
1180 enough case that it is useful to keep early-lrz test against
2226 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
2227 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
2238 <!-- Same as above but different name??: -->
2239 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
2240 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
2244 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
2251 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
2252 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
2257 <!--
2260 -->
2269 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
2270 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
2271 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
2272 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
2273 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
2274 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
2275 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
2276 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
2277 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
2278 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
2297 <!-- Crashdumper writes -->
2299 <!-- Crashdumper reads -->
2302 <!-- 4 is unknown -->
2304 <!-- RPTR shadow writes -->
2306 <!-- Memory accesses from PM4 packets in the ringbuffer -->
2308 <!-- Ringbuffer reads -->
2310 <!-- Instruction cache fetches -->
2313 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
2315 <!-- all the threshold values seem to be in units of quad-dwords: -->
2341 <!-- total ROQ size: -->
2366 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
2368 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
2386 <!-- SDS == CP_SET_DRAW_STATE: -->
2389 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
2392 <!--
2395 -->
2448 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
2450 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
2452 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
2453 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
2454 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
2455 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
2456 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
2457 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
2458 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
2459 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
2460 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
2461 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
2462 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
2463 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
2464 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
2466 <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
2467 <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
2468 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
2469 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
2471 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
2472 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
2473 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
2474 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
2475 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
2476 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
2477 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
2479 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
2481 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
2482 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
2483 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
2487 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
2488 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
2489 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
2491 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
2492 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
2493 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
2494 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
2495 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
2496 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
2497 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
2498 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
2499 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
2500 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
2501 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
2502 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
2540 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
2541 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
2542 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
2543 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
2544 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
2545 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
2547 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
2548 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
2567 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
2568 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
2569 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
2570 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
2571 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
2572 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
2573 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
2574 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
2575 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
2576 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
2577 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
2578 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
2579 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
2580 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
2581 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
2582 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
2583 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
2584 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
2585 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
2586 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
2587 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
2588 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
2589 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
2590 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
2591 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
2592 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
2593 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
2594 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
2609 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
2611 <!---
2615 -->
2617 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
2619 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
2621 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
2623 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
2625 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
2627 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
2629 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
2631 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
2633 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
2635 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
2645 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
2654 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
2655 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
2659 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
2665 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
2773 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
2774 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
2778 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
2790 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
2955 <!--
2958 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
2963 LIMIT is set to PITCH - 64, to make room for a bit of overflow
2964 -->
2999 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
3001 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
3002 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
3003 <!-- always 0x03200000 ? -->
3006 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
3017 <!-- controls near z clip behavior (set for vulkan) -->
3019 <!-- guess based on a3xx and meaning of bits 8 and 9
3020 if the guess is right then this is related to point sprite clipping -->
3036 <!-- see also RB_RENDER_CONTROL0 -->
3044 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
3045 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
3052 <!-- Something connected to depth-stencil attachment size -->
3053 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
3055 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
3057 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
3058 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
3059 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
3060 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
3062 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
3064 <!-- 0x8006-0x800f invalid -->
3087 <!--
3096 -->
3107 <!-- 0x8093 invalid -->
3114 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
3138 <!-- 0x809e/0x809f invalid -->
3152 flushed before the data or vice-versa, leading to
3157 non-coherent blending.
3172 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
3178 <!-- I'm guessing this is the same as a3xx -->
3192 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
3212 <!-- We don't have a flag type and this flags combination is often used -->
3263 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
3265 <!-- 0x80a7-0x80ae invalid -->
3284 <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
3285 <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
3286 <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
3287 <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
3288 <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
3289 <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
3290 <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
3306 - 0.0 if GREATER
3307 - 1.0 if LESS
3310 <!-- set when depth-test + depth-write enabled -->
3315 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
3321 If DIR_WRITE is not enabled - there is no write to direction buffer.
3324 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
3342 <!-- TODO: fix the shr fields -->
3347 <!--
3370 // fast-clear buffer is 1bit/block:
3376 -->
3378 <!-- 0x8108 invalid -->
3382 <!--
3388 the value stored in the LRZ buffer, if not - LRZ is disabled.
3389 -->
3396 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">
3401 <!-- 0x810c-0x810f invalid -->
3405 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
3406 <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
3408 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3413 <!-- Always written together and always equal 09510840 00000a62 -->
3414 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
3415 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
3417 <!-- 0x8112-0x83ff invalid -->
3436 <!-- required when blitting D24S8/D24X8 -->
3438 <!-- some sort of channel mask, disabled channels are set to zero ? -->
3442 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
3446 <!-- note: the low 8 bits for src coords are valid, probably fixed point
3449 -->
3461 <!-- 0x840c-0x85ff invalid -->
3463 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
3469 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
3474 <!-- note 0x8620-0x87ff are not all invalid
3475 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
3476 -->
3478 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
3488 <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
3499 <!-- set during binning pass: -->
3506 <!-- bit seems to be set whenever depth buffer enabled: -->
3508 <!-- bitmask of MRTs using UBWC flag buffer: -->
3511 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3513 <!-- set during binning pass: -->
3520 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3537 <!-- 0x8807-0x8808 invalid -->
3538 <!--
3541 -->
3543 <!-- see also GRAS_CNTL -->
3554 <!-- enable bits for various FS sysvalue regs: -->
3595 <!-- Same as SP_SRGB_CNTL -->
3610 <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
3611 <!-- 0x8813-0x8817 invalid -->
3612 <!-- always 0x0 ? -->
3614 <!-- 0x8819-0x881e all 32 bits -->
3621 <!-- 0x881f invalid -->
3644 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
3650 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3652 <!--
3655 -->
3658 <!--
3663 -->
3664 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
3680 <!-- per-mrt enable bit -->
3688 <!-- 0x8866-0x886f invalid -->
3708 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
3713 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
3714 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3728 <!-- 0x887a-0x887f invalid -->
3732 <!--
3737 -->
3755 <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
3776 <!-- 0x888a-0x888f invalid -->
3782 <!-- 0x8892-0x8897 invalid -->
3786 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
3787 <!-- 0x8899-0x88bf invalid -->
3788 <!-- clamps depth value for depth test/write -->
3791 <!-- 0x88c2-0x88cf invalid-->
3798 <!-- weird to duplicate other regs from same block?? -->
3808 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
3816 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3820 <!-- array-pitch is size of layer -->
3833 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
3835 …bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color resto…
3836 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
3837 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
3838 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
3841 1 - depth
3842 2 - stencil
3843 3 - depth+stencil
3848 <!-- set when this is the last resolve on a650+ -->
3850 <!--
3855 -->
3858 <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
3859 <!-- Value conditioned based on predicate, changed before blits -->
3869 <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
3873 <!-- GMEM offset of CCU depth cache -->
3876 <!-- GMEM offset of CCU color cache
3881 -->
3884 <!-- 0x88e6-0x88ef invalid -->
3885 <!-- always 0x0 ? -->
3887 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
3894 <!-- Connected to VK_EXT_fragment_density_map? -->
3895 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
3896 <!-- 0x88f6-0x88ff invalid -->
3900 <!-- TODO: actually part of array pitch -->
3911 <!-- 0x891b-0x8926 invalid -->
3917 <!-- 0x8929-0x89ff invalid -->
3919 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
3921 <!--
3923 blob writing non-zero:
3924 -->
3949 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/>
3959 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/>
3962 <!-- 0x8c02-0x8c16 invalid -->
3966 <!-- this is a guess but seems likely (for NV12/IYUV): -->
3973 <!-- this is a guess but seems likely (for NV12 with UBWC): -->
3977 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
3978 <!-- unlike a5xx, these are per channel values rather than packed -->
3984 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
3986 <!-- 0x8c35-0x8dff invalid -->
3988 <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
3990 <!-- 0x8e00-0x8e03 invalid -->
3991 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
3993 <!-- 0x02080000 in GMEM, zero otherwise? -->
3994 <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
3998 <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
4003 <!-- GMEM offset of CCU depth cache -->
4006 <!-- GMEM offset of CCU color cache
4011 -->
4013 <!--TODO: valid mask 0xfffffc1f -->
4015 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
4018 <!-- rest of the bits were moved to RB_CCU_CNTL2 -->
4023 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
4029 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
4030 <!-- 0x8e09-0x8e0f invalid -->
4033 <!-- 0x8e1d-0x8e1f invalid -->
4034 <!-- 0x8e20-0x8e25 more perfcntr sel? -->
4035 <!-- 0x8e26-0x8e27 invalid -->
4037 <!-- 0x8e29-0x8e2b invalid -->
4039 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
4042 <!-- 0x8e3e-0x8e4f invalid -->
4043 <!-- GMEM save/restore for preemption: -->
4045 <!-- address for GMEM save/restore? -->
4047 <!-- 0x8e53-0x8e7f invalid -->
4048 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
4049 <!-- 0x8e80-0x8e83 are valid -->
4050 <!-- 0x8e84-0x90ff invalid -->
4052 <!-- 0x9000-0x90ff invalid -->
4060 <!-- there can be up to 8 total clip/cull distance outputs,
4063 -->
4078 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
4090 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
4115 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
4127 Multi-position output lets the last geometry
4137 …<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" u…
4138 …<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" u…
4139 …<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usa…
4140 …<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage…
4156 <!-- 0x9109-0x91ff invalid -->
4166 <!-- always 0x0 -->
4171 <!-- one bit per varying component: -->
4176 <!--
4196 This field is auto-incremented when VPC_SO_PROG is
4198 -->
4200 <!-- clear all A_EN and B_EN bits for all DWORD's -->
4203 <!-- special register, write multiple times to load SO program (not readable) -->
4226 <!-- 0x9237-0x92ff invalid -->
4227 <!-- always 0x0 ? -->
4233 plus # of transform-feedback (streamout) varyings if using the
4242 number of views minus one when multi-position
4253 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
4261 strictly required for multi-position output,
4263 views at once, but it can be used when multi-pos
4271 <!--
4273 -->
4283 <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
4286 <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4289 <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
4292 <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4296 <!-- 0x9307-0x95ff invalid -->
4298 <!-- TODO: 0x9600-0x97ff range -->
4299 …set="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -…
4301 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
4304 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
4305 <!-- 0x960a-0x9623 invalid -->
4306 <!-- TODO: regs from 0x9624-0x963a -->
4307 <!-- 0x963b-0x97ff invalid -->
4311 <!-- always 0x0 ? -->
4331 <!-- New in a6xx gen3+ -->
4339 <!-- 0x980b-0x983f invalid -->
4341 <!-- 0x9840 - 0x9842 are not readable -->
4351 <!-- I think only the low bit is actually used? -->
4356 <!--
4360 -->
4363 <!-- 0x9843-0x997f invalid -->
4368 <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
4373 <!-- which stream to send to GRAS -->
4375 <!-- discard primitives before rasterization -->
4378 <!-- VPC_RASTER_CNTL -->
4379 <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
4380 <!-- which stream to send to GRAS -->
4382 <!-- discard primitives before rasterization -->
4385 <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
4386 <!-- which stream to send to GRAS -->
4388 <!-- discard primitives before rasterization -->
4392 <!-- Both are a750+.
4394 -->
4395 <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
4396 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
4398 -->
4399 <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
4401 <!-- 0x9982-0x9aff invalid -->
4408 plus # of transform-feedback (streamout) varyings if using the
4415 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
4418 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
4423 <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
4431 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
4437 <!-- mask of enabled views, doesn't exist on A630 -->
4439 <!-- 0x9b09-0x9bff invalid -->
4441 <!-- special register (but note first 8 bits can be written/read) -->
4445 <!-- 0x9c01-0x9dff invalid -->
4446 <!-- TODO: 0x9e00-0xa000 range incomplete -->
4453 …<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage…
4464 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
4478 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
4481 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
4483 <!-- always 0x0 -->
4494 <!-- only used for VS in non-multi-position-output case -->
4502 patch within the HS->DS buffers. When a draw is
4524 <!--
4526 -->
4536 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
4538 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
4551 <!-- IDX and byte OFFSET into VFD_FETCH -->
4556 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
4571 <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
4575 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
4577 <!--
4580 -->
4587 <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
4589 <!--
4592 - used (half): 0-15 68-179 (cnt=128, max=179)
4593 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
4597 - used (merged): 0-191 (cnt=192, max=191)
4602 -->
4605 <!-- could it be a low bit of branchstack? -->
4607 <!-- seems to be nesting level for flow control:.. -->
4612 <!--
4615 -->
4622 <!--
4625 -->
4632 <!-- # of VS outputs including pos/psize -->
4634 <!-- FLAGS_REGID only for GS -->
4639 <!--
4642 -->
4644 <!--
4645 Creates a separate preamble-only thread?
4648 - Only shared, a1, and consts regs could be used
4650 - No cat5/cat6, only stc/ldc variants are working;
4651 - Values writen to shared regs are not accessible by the rest
4653 - Instructions before shps are also considered to be a part of
4658 -->
4661 <!-- bitmask of true/false conditions for VS brac.N instructions,
4662 bit N corresponds to brac.N -->
4664 <!-- # of VS outputs including pos/psize -->
4674 <!--
4680 -->
4714 - stp/ldp offset
4715 - fiber id
4716 - wavefront id (a swizzled version of what "getwid" returns)
4717 - SP ID (the same as what "getspid" returns)
4720 TOTALPVTMEMSIZE. In the per-wave layout, the
4723 - offset % 4 (offset within dword)
4724 - fiber id
4725 - offset / 4
4726 - wavefront id
4727 - SP ID
4731 wavefront). In the per-fiber layout, the indices
4734 - offset
4735 - fiber id % 4
4736 - wavefront id
4737 - fiber id / 4
4738 - SP ID
4744 with per-fiber layout. The blob will fall back
4745 to per-wave instead.
4755 stack seems to be after all the normal per-SP private
4770 <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4773 <!-- There is no mergedregs bit, that comes from the VS. -->
4776 <!--
4781 -->
4785 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4795 <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4798 <!-- There is no mergedregs bit, that comes from the VS. -->
4803 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4822 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4832 <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4835 <!-- There is no mergedregs bit, that comes from the VS. -->
4843 size less than 63 - size
4844 size of 63 (?) or 64 - 63
4845 size greater than 64 - 64
4847 What to program when the size is 61-63 is a guess, but
4854 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4874 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4884 <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4895 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
4907 <!-- note: vk blob uses bit24 -->
4929 <!-- per-mrt enable bit -->
4936 <!-- Same as RB_SRGB_CNTL -->
4997 <!-- Blob never uses it -->
4998 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
5014 …<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit…
5015 <reg32 offset="0" name="CMD" variants="A7XX-">
5033 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
5036 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
5043 <!-- seems to make SP use less concurrent threads when possible? -->
5045 <!-- has a small impact on performance, not clear what it does -->
5051 <!-- set for compute shaders -->
5055 If 0 - all 32k of shared storage is enabled, otherwise
5059 64k (and has 36k of storage on A640 - reads between 36k-64k
5064 <!-- always 1 ? -->
5077 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
5078 <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
5080 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
5087 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
5089 <!-- gl_LocalInvocationIndex -->
5091 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5092 one of those 6 "SP cores" -->
5094 <!-- Must match SP_CS_CTRL -->
5096 <!-- 1 thread per wave (ignored if bit9 set) -->
5100 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
5101 <!-- gl_LocalInvocationIndex -->
5103 <!-- Must match SP_CS_CTRL -->
5105 <!-- 1 thread per wave (would hang if THREAD128 is also set) -->
5108 <!-- Affects getone. If enabled, getone sometimes executed 1? less times
5110 -->
5114 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
5136 …<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cm…
5137 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5143 <!--
5145 -->
5149 <!-- Correlated with avgs/uvgs usage in FS -->
5150 <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
5152 <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
5155 <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
5180 <!--
5183 out-of-bounds isam/isamm. GL and Vulkan robustness require us to
5184 return 0 on out-of-bound textureFetch().
5185 -->
5192 <!--
5194 load a 32-bit value (so hc0.y loads the same value as c0.y)
5199 -->
5202 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
5205 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
5206 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
5217 …<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_bl…
5218 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5224 <!--
5227 -->
5231 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
5237 <!-- looks like HW only cares about the base type of this format,
5238 which matches the ifmt? -->
5240 <!-- set when ifmt is R2D_UNORM8_SRGB -->
5242 <!-- some sort of channel mask, not sure what it is for -->
5247 …<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage…
5252 <!-- TODO: valid bits 0x3c3f, see kernel -->
5259 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
5260 <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
5261 <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
5262 <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
5265 <!-- some perfcntrs are affected by a per-stage enable bit
5267 TODO: verify position of HS/DS/GS bits -->
5276 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
5277 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
5278 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
5279 <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
5280 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
5287 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
5288 <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
5289 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
5290 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
5291 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
5294 <!--
5298 -->
5306 <!-- could be all the stuff below here is actually TPL1?? -->
5317 <!-- looks to work in the same way as a5xx: -->
5327 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
5329 <!--
5333 -->
5345 …<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usag…
5350 …<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_bl…
5356 <!-- planes for NV12, etc. (TODO: not tested) -->
5361 <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
5362 …t="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>
5363 <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
5368 …<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage=…
5369 …="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>
5382 <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
5383 …<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"…
5385 <!-- always 0x100000 or 0x1000000? -->
5389 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set
5390 and if other blit is done without it - UBWC image may be copied incorrectly.
5391 -->
5397 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
5401 …NOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
5418 <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
5423 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
5431 …<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5432 …<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5433 …<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5434 …<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5436 <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
5437 <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
5441 <!-- Always 0 -->
5442 <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
5444 <!-- Used in VK_KHR_fragment_shading_rate -->
5445 <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
5447 <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
5449 <!-- UNK8 is set on a730/a740 -->
5451 <!-- UNK9 is set on a750 -->
5461 <!-- must match SP_FS_CTRL -->
5467 <!-- register loaded with position (bary.f) -->
5485 …b981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
5487 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
5489 the hardware will simply emit smaller waves when it runs out of space. -->
5494 <!-- SAMPLEID is loaded into a half-precision register: -->
5503 …<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp…
5504 <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
5507 <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
5509 <!-- SAMPLEID is loaded into a half-precision register: -->
5514 …<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" u…
5515 …<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" u…
5516 …<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" u…
5517 <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
5519 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5522 <!-- localsize is value minus one: -->
5546 <!-- these are all vec3. first 3 need to be high regs
5549 -->
5556 <!-- gl_LocalInvocationIndex -->
5558 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5559 one of those 6 "SP cores" -->
5561 <!-- Must match SP_CS_CTRL -->
5563 <!-- 1 thread per wave (ignored if bit9 set) -->
5566 <!--note: vulkan blob doesn't use these -->
5571 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5572 <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
5574 <!-- localsize is value minus one: -->
5579 <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
5582 <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
5585 <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
5588 <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
5591 <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
5594 <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
5597 <!--note: vulkan blob doesn't use these -->
5598 <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
5599 <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
5600 <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
5609 <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
5610 <!-- gl_LocalInvocationIndex -->
5612 <!-- Must match SP_CS_CTRL -->
5620 <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
5621 <!-- localsize is value minus one: -->
5631 <!-- mirror of SP_CS_BINDLESS_BASE -->
5639 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
5643 <!-- always 1 ? -->
5656 <!-- I think only the low bit is actually used? -->
5668 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5679 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
5683 <!-- SS6_BINDLESS: one bit per bindless base -->
5688 <reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">
5692 <reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">
5696 <reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">
5701 <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
5708 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5719 <!-- SS6_BINDLESS: one bit per bindless base -->
5725 …<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5727 <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
5735 c504-c511 in each stage. Both VS and FS shared consts
5751 <!-- mirror of SP_BINDLESS_BASE -->
5764 …xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
5771 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
5774 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
5776 <!-- Don't know if these are SP, always 0 -->
5777 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
5778 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
5779 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
5781 <!--
5784 - write EVENT_CMD pipe register
5785 - write CP_EVENT_START
5786 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
5787 - write PC_EVENT_CMD with event or PC_DRAW_CMD
5788 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
5789 - write PC_EVENT_CMD(CONTEXT_DONE)
5790 - write CP_EVENT_END
5792 -->
5807 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
5810 <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
5814 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
5816 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
5823 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
5844 … name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
5850 [-1, 1] if the format is snorm, *after*
5871 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
5879 <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
5894 <!-- overlaps with MIPLVLS -->
5899 <!--
5900 Why is the swap needed in addition to SWIZ_*? The swap
5903 -->
5904 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
5909 <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>
5912 <!--
5915 -->
5920 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
5927 <!--
5932 -->
5935 <!--
5939 -->
5943 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
5944 the address of the non-flag base buffer is determined automatically,
5946 -->
5955 <!-- overlaps with PLANE_PITCH -->
5957 <!-- pitch for plane 2 / plane 3 -->
5960 <!-- 7/8 is plane 2 address for planar formats -->
5967 <!-- 9/10 is plane 3 address for planar formats -->
5973 <!-- log2 size of the first level, required for mipmapping -->
5990 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
6079 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
6080 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">