Lines Matching +full:sense +full:- +full:bitfield +full:- +full:width
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
9 <!--
12 - "cmd" - the register is used outside of renderpass and blits,
14 - "rp_blit" - the register is used inside renderpass or blits
21 -->
23 <!-- these might be same as a5xx -->
39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
121 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
122 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
123 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
125 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
129 <!-- Note: tiling/UBWC for these may be different from equivalent formats
131 -->
180 <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
183 <!-- Not a hw enum, used internally in driver -->
188 <!-- probably same as a5xx -->
203 <bitfield name="BASE_ADDR" low="0" high="17"/>
204 <bitfield name="MASK_LEN" low="18" high="30"/>
205 <bitfield name="READ" pos="31" type="boolean"/>
1121 <!--
1137 -->
1150 <doc>Allow early z-test and early-lrz (if applicable)</doc>
1152 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
1155 A special mode that allows early-lrz test but disables
1156 early-z test. Which might sound a bit funny, since
1157 lrz-test happens before z-test. But as long as a couple
1158 conditions are maintained this allows using lrz-test in
1161 1) Disable lrz-write in cases where it is uncertain during
1163 shader has-kill, writes-z, or alpha/stencil test is
1164 enabled. (For correctness, lrz-write must be disabled
1166 z-prepass works.
1168 2) Disable lrz-write and test if a depth-test direction
1173 lrz-test. But geometry which may be (or contributes to
1174 blend) will pass the lrz-test.
1176 This allows us to keep early-lrz-test in cases where the frag
1177 shader does not write-z (ie. we know the z-value before FS)
1178 and does not have side-effects (image/ssbo writes, etc), but
1180 enough case that it is useful to keep early-lrz test against
2222 <domain name="A6XX" width="32" prefix="variant" varset="chip">
2224 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
2225 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
2226 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
2227 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
2228 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
2229 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
2230 <bitfield name="CP_SW" pos="8" type="boolean"/>
2231 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
2232 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
2233 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
2234 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
2235 <bitfield name="CP_IB2" pos="13" type="boolean"/>
2236 <bitfield name="CP_IB1" pos="14" type="boolean"/>
2237 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
2238 <!-- Same as above but different name??: -->
2239 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
2240 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
2241 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
2242 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
2243 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
2244 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
2245 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
2246 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
2247 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
2248 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
2249 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
2250 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
2251 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
2252 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
2253 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
2254 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
2257 <!--
2260 -->
2262 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
2263 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
2264 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
2265 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
2266 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
2267 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
2268 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
2269 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
2270 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
2271 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
2272 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
2273 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
2274 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
2275 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
2276 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
2277 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
2278 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
2288 <bitfield name="IFPC" pos="0" type="boolean"/>
2297 <!-- Crashdumper writes -->
2298 <bitfield pos="6" name="CDWRITE" type="boolean"/>
2299 <!-- Crashdumper reads -->
2300 <bitfield pos="5" name="CDREAD" type="boolean"/>
2302 <!-- 4 is unknown -->
2304 <!-- RPTR shadow writes -->
2305 <bitfield pos="3" name="RBRPWB" type="boolean"/>
2306 <!-- Memory accesses from PM4 packets in the ringbuffer -->
2307 <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
2308 <!-- Ringbuffer reads -->
2309 <bitfield pos="1" name="RBFETCH" type="boolean"/>
2310 <!-- Instruction cache fetches -->
2311 <bitfield pos="0" name="ICACHE" type="boolean"/>
2313 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
2315 <!-- all the threshold values seem to be in units of quad-dwords: -->
2323 <bitfield name="MRB_START" low="0" high="7" shr="2"/>
2324 <bitfield name="VSD_START" low="8" high="15" shr="2"/>
2325 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
2326 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
2340 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
2341 <!-- total ROQ size: -->
2342 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
2349 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
2350 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
2351 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
2366 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
2368 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
2386 <!-- SDS == CP_SET_DRAW_STATE: -->
2389 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
2392 <!--
2395 -->
2399 <bitfield name="RPTR" low="0" high="9"/>
2400 <bitfield name="WPTR" low="16" high="25"/>
2417 <bitfield name="REM" low="16" high="31"/>
2421 <bitfield name="REM" low="16" high="31"/>
2425 <bitfield name="REM" low="16" high="31"/>
2429 <bitfield name="REM" low="16" high="31"/>
2433 <bitfield name="REM" low="16" high="31"/>
2437 <bitfield name="REM" low="16" high="31"/>
2441 <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
2442 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
2443 <bitfield name="CONTEXT" low="4" high="5"/>
2448 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
2450 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
2452 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
2453 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
2454 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
2455 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
2456 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
2457 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
2458 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
2459 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
2460 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
2461 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
2462 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
2463 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
2464 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
2466 <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
2467 <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
2468 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
2469 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
2471 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
2472 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
2473 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
2474 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
2475 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
2476 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
2477 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
2479 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
2481 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
2482 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
2483 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
2487 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
2488 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
2489 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
2491 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
2492 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
2493 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
2494 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
2495 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
2496 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
2497 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
2498 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
2499 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
2500 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
2501 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
2502 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
2508 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
2509 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
2510 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
2511 <bitfield pos="20" name="VSC_BUSY" type="boolean"/>
2512 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
2513 <bitfield pos="18" name="SP_BUSY" type="boolean"/>
2514 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
2515 <bitfield pos="16" name="VPC_BUSY" type="boolean"/>
2516 <bitfield pos="15" name="VFD_BUSY" type="boolean"/>
2517 <bitfield pos="14" name="TESS_BUSY" type="boolean"/>
2518 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
2519 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
2520 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
2521 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
2522 <bitfield pos="9" name="A2D_BUSY" type="boolean"/>
2523 <bitfield pos="8" name="CCU_BUSY" type="boolean"/>
2524 <bitfield pos="7" name="RB_BUSY" type="boolean"/>
2525 <bitfield pos="6" name="RAS_BUSY" type="boolean"/>
2526 <bitfield pos="5" name="TSE_BUSY" type="boolean"/>
2527 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
2528 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
2529 <bitfield pos="2" name="CP_BUSY" type="boolean"/>
2530 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
2531 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
2536 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
2540 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
2541 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
2542 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
2543 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
2544 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
2545 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
2547 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
2548 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
2567 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
2568 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
2569 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
2570 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
2571 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
2572 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
2573 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
2574 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
2575 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
2576 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
2577 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
2578 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
2579 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
2580 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
2581 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
2582 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
2583 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
2584 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
2585 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
2586 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
2587 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
2588 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
2589 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
2590 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
2591 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
2592 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
2593 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
2594 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
2609 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
2611 <!---
2615 -->
2617 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
2619 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
2621 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
2623 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
2625 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
2627 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
2629 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
2631 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
2633 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
2635 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
2645 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
2651 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
2654 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
2655 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
2659 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
2665 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
2773 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
2774 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
2778 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
2779 <bitfield name="TXDONE" pos="0" type="boolean"/>
2790 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
2797 <bitfield high="7" low="0" name="PING_INDEX"/>
2798 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
2801 <bitfield high="5" low="0" name="TRACEEN"/>
2802 <bitfield high="14" low="12" name="GRANU"/>
2803 <bitfield high="31" low="28" name="SEGT"/>
2806 <bitfield high="27" low="24" name="ENABLE"/>
2817 <bitfield high="3" low="0" name="BYTEL0"/>
2818 <bitfield high="7" low="4" name="BYTEL1"/>
2819 <bitfield high="11" low="8" name="BYTEL2"/>
2820 <bitfield high="15" low="12" name="BYTEL3"/>
2821 <bitfield high="19" low="16" name="BYTEL4"/>
2822 <bitfield high="23" low="20" name="BYTEL5"/>
2823 <bitfield high="27" low="24" name="BYTEL6"/>
2824 <bitfield high="31" low="28" name="BYTEL7"/>
2827 <bitfield high="3" low="0" name="BYTEL8"/>
2828 <bitfield high="7" low="4" name="BYTEL9"/>
2829 <bitfield high="11" low="8" name="BYTEL10"/>
2830 <bitfield high="15" low="12" name="BYTEL11"/>
2831 <bitfield high="19" low="16" name="BYTEL12"/>
2832 <bitfield high="23" low="20" name="BYTEL13"/>
2833 <bitfield high="27" low="24" name="BYTEL14"/>
2834 <bitfield high="31" low="28" name="BYTEL15"/>
2843 <bitfield name="BINNING" pos="0" type="boolean"/>
2857 <bitfield high="7" low="0" name="PERFSEL"/>
2865 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
2873 <bitfield low="0" high="3" name="DATA_SEL"/>
2877 <bitfield low="0" high="8" name="DATA_SEL"/>
2931 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
2932 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
2936 <bitfield name="NX" low="1" high="10" type="uint"/>
2937 <bitfield name="NY" low="11" high="20" type="uint"/>
2949 <bitfield name="X" low="0" high="9" type="uint"/>
2950 <bitfield name="Y" low="10" high="19" type="uint"/>
2951 <bitfield name="W" low="20" high="25" type="uint"/>
2952 <bitfield name="H" low="26" high="31" type="uint"/>
2955 <!--
2958 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
2963 LIMIT is set to PITCH - 64, to make room for a bit of overflow
2964 -->
2999 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
3001 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
3002 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
3003 <!-- always 0x03200000 ? -->
3006 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
3008 <bitfield name="X" low="0" high="13" type="uint"/>
3009 <bitfield name="Y" low="16" high="29" type="uint"/>
3013 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
3014 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
3015 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
3016 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
3017 <!-- controls near z clip behavior (set for vulkan) -->
3018 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
3019 <!-- guess based on a3xx and meaning of bits 8 and 9
3020 if the guess is right then this is related to point sprite clipping -->
3021 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
3022 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
3023 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
3027 <bitfield name="CLIP_MASK" low="0" high="7"/>
3028 <bitfield name="CULL_MASK" low="8" high="15"/>
3036 <!-- see also RB_RENDER_CONTROL0 -->
3037 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
3038 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
3039 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
3040 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
3041 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
3042 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
3043 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
3044 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
3045 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
3048 <bitfield name="HORZ" low="0" high="8" type="uint"/>
3049 <bitfield name="VERT" low="10" high="18" type="uint"/>
3052 <!-- Something connected to depth-stencil attachment size -->
3053 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
3055 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
3057 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
3058 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
3059 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
3060 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
3062 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
3064 <!-- 0x8006-0x800f invalid -->
3079 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
3080 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
3081 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
3082 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
3083 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
3084 <bitfield name="UNK12" pos="12"/>
3085 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
3086 <bitfield name="UNK15" low="15" high="16"/>
3087 <!--
3096 -->
3097 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
3098 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
3099 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
3100 <bitfield name="UNK20" low="20" high="22"/>
3103 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
3104 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
3107 <!-- 0x8093 invalid -->
3109 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3114 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
3116 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3117 <bitfield name="UNK3" pos="3"/>
3121 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
3122 <bitfield name="SHIFTAMOUNT" low="1" high="2"/>
3123 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
3124 <bitfield name="UNK4" low="4" high="5"/>
3127 <bitfield name="UNK0" pos="0" type="boolean"/>
3128 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
3132 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
3133 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
3138 <!-- 0x809e/0x809f invalid -->
3152 flushed before the data or vice-versa, leading to
3157 non-coherent blending.
3172 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
3178 <!-- I'm guessing this is the same as a3xx -->
3187 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
3188 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
3189 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
3190 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
3191 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
3192 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
3193 <bitfield name="UNK9" pos="9" type="boolean"/>
3194 <bitfield name="ROTATION" low="10" high="11" type="uint"/>
3195 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
3212 <!-- We don't have a flag type and this flags combination is often used -->
3218 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3219 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3220 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3222 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
3223 …<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
3229 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3230 <bitfield name="UNK27" pos="27"/>
3234 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3235 <bitfield name="UNK2" pos="2"/>
3236 <bitfield name="UNK3" pos="3"/>
3239 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3240 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3244 <bitfield name="UNK0" pos="0"/>
3245 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
3249 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
3250 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
3251 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
3252 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
3253 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
3254 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
3255 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
3256 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
3263 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
3265 <!-- 0x80a7-0x80ae invalid -->
3269 <bitfield name="X" low="0" high="15" type="uint"/>
3270 <bitfield name="Y" low="16" high="31" type="uint"/>
3284 <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
3285 <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
3286 <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
3287 <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
3288 <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
3289 <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
3290 <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
3299 <bitfield name="ENABLE" pos="0" type="boolean"/>
3301 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
3303 <bitfield name="GREATER" pos="2" type="boolean"/>
3306 - 0.0 if GREATER
3307 - 1.0 if LESS
3309 <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
3310 <!-- set when depth-test + depth-write enabled -->
3311 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
3312 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
3313 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
3315 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
3318 <bitfield name="DIR_WRITE" pos="8" type="boolean"/>
3321 If DIR_WRITE is not enabled - there is no write to direction buffer.
3323 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
3324 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
3333 <bitfield name="SAMPLEID" pos="0" type="boolean"/>
3334 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
3338 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3342 <!-- TODO: fix the shr fields -->
3343 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
3344 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
3347 <!--
3357 width *= 2;
3363 lrz_width = div_round_up(width, 8);
3370 // fast-clear buffer is 1bit/block:
3376 -->
3378 <!-- 0x8108 invalid -->
3380 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
3382 <!--
3388 the value stored in the LRZ buffer, if not - LRZ is disabled.
3389 -->
3391 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
3392 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
3393 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
3396 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">
3397 <bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/>
3398 <bitfield name="FC_ENABLE" pos="1" type="boolean"/>
3401 <!-- 0x810c-0x810f invalid -->
3405 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
3406 <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
3408 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3409 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3410 <bitfield name="UNK3" pos="3"/>
3413 <!-- Always written together and always equal 09510840 00000a62 -->
3414 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
3415 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
3417 <!-- 0x8112-0x83ff invalid -->
3429 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
3430 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
3431 <bitfield name="UNK4" low="4" high="6"/>
3432 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
3433 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
3434 <bitfield name="SCISSOR" pos="16" type="boolean"/>
3435 <bitfield name="UNK17" low="17" high="18"/>
3436 <!-- required when blitting D24S8/D24X8 -->
3437 <bitfield name="D24S8" pos="19" type="boolean"/>
3438 <!-- some sort of channel mask, disabled channels are set to zero ? -->
3439 <bitfield name="MASK" low="20" high="23"/>
3440 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
3441 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
3442 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
3446 <!-- note: the low 8 bits for src coords are valid, probably fixed point
3449 -->
3461 <!-- 0x840c-0x85ff invalid -->
3463 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
3465 <bitfield name="UNK7" pos="7" type="boolean"/>
3466 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
3469 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
3474 <!-- note 0x8620-0x87ff are not all invalid
3476 -->
3478 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
3480 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3481 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3482 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3483 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
3484 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
3485 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3488 <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
3489 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3490 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3491 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3492 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
3493 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3497 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
3498 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
3499 <!-- set during binning pass: -->
3500 <bitfield name="BINNING" pos="7" type="boolean"/>
3501 <bitfield name="UNK8" low="8" high="10"/>
3502 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
3503 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
3504 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
3505 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
3506 <!-- bit seems to be set whenever depth buffer enabled: -->
3507 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
3508 <!-- bitmask of MRTs using UBWC flag buffer: -->
3509 <bitfield name="FLAG_MRTS" low="16" high="23"/>
3511 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3512 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
3513 <!-- set during binning pass: -->
3514 <bitfield name="BINNING" pos="7" type="boolean"/>
3515 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
3516 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
3517 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
3518 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
3520 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3521 <bitfield name="BINNING" pos="7" type="boolean"/>
3525 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3526 <bitfield name="UNK2" pos="2"/>
3527 <bitfield name="UNK3" pos="3"/>
3530 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3531 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
3537 <!-- 0x8807-0x8808 invalid -->
3538 <!--
3541 -->
3543 <!-- see also GRAS_CNTL -->
3544 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
3545 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
3546 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
3547 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
3548 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
3549 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
3550 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
3551 <bitfield name="UNK10" pos="10" type="boolean"/>
3554 <!-- enable bits for various FS sysvalue regs: -->
3555 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
3556 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
3557 <bitfield name="FACENESS" pos="2" type="boolean"/>
3558 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
3559 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
3560 <bitfield name="CENTERRHW" pos="6" type="boolean"/>
3561 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
3562 <bitfield name="FOVEATION" pos="8" type="boolean"/>
3566 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3567 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
3568 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
3569 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
3572 <bitfield name="MRT" low="0" high="3" type="uint"/>
3575 <bitfield name="RT0" low="0" high="3"/>
3576 <bitfield name="RT1" low="4" high="7"/>
3577 <bitfield name="RT2" low="8" high="11"/>
3578 <bitfield name="RT3" low="12" high="15"/>
3579 <bitfield name="RT4" low="16" high="19"/>
3580 <bitfield name="RT5" low="20" high="23"/>
3581 <bitfield name="RT6" low="24" high="27"/>
3582 <bitfield name="RT7" low="28" high="31"/>
3585 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
3586 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
3587 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
3588 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
3589 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
3590 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
3591 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
3592 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
3595 <!-- Same as SP_SRGB_CNTL -->
3596 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3597 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3598 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3599 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3600 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3601 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3602 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3603 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3607 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
3610 <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
3611 <!-- 0x8813-0x8817 invalid -->
3612 <!-- always 0x0 ? -->
3614 <!-- 0x8819-0x881e all 32 bits -->
3621 <!-- 0x881f invalid -->
3624 <bitfield name="BLEND" pos="0" type="boolean"/>
3625 <bitfield name="BLEND2" pos="1" type="boolean"/>
3626 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
3627 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
3628 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
3631 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
3632 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
3633 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
3634 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
3635 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
3636 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
3639 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3640 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3641 <bitfield name="UNK10" pos="10"/>
3642 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
3644 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
3645 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3646 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3647 <bitfield name="UNK10" pos="10"/>
3648 <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/>
3649 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
3650 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3652 <!--
3655 -->
3658 <!--
3663 -->
3664 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
3675 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
3676 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
3677 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
3680 <!-- per-mrt enable bit -->
3681 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
3682 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
3683 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3684 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3685 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
3686 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
3688 <!-- 0x8866-0x886f invalid -->
3690 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3694 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
3695 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
3696 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
3697 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
3702 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
3703 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
3706 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
3708 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
3710 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3711 <bitfield name="UNK3" low="3" high="4"/>
3713 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
3714 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3715 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3716 <bitfield name="UNK3" low="3" high="4"/>
3717 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
3718 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>
3728 <!-- 0x887a-0x887f invalid -->
3730 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
3731 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
3732 <!--
3737 -->
3738 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
3739 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
3740 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
3741 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
3742 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
3743 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
3744 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
3745 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
3746 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
3749 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
3752 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
3753 <bitfield name="UNK1" pos="1" type="boolean"/>
3755 <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
3756 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
3757 <bitfield name="UNK1" pos="1" type="boolean"/>
3758 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>
3765 <bitfield name="REF" low="0" high="7"/>
3766 <bitfield name="BFREF" low="8" high="15"/>
3769 <bitfield name="MASK" low="0" high="7"/>
3770 <bitfield name="BFMASK" low="8" high="15"/>
3773 <bitfield name="WRMASK" low="0" high="7"/>
3774 <bitfield name="BFWRMASK" low="8" high="15"/>
3776 <!-- 0x888a-0x888f invalid -->
3779 <bitfield name="DISABLE" pos="0" type="boolean"/>
3780 <bitfield name="COPY" pos="1" type="boolean"/>
3782 <!-- 0x8892-0x8897 invalid -->
3784 <bitfield name="ENABLE" pos="0" type="boolean"/>
3786 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
3787 <!-- 0x8899-0x88bf invalid -->
3788 <!-- clamps depth value for depth test/write -->
3791 <!-- 0x88c2-0x88cf invalid-->
3793 <bitfield name="UNK0" low="0" high="12"/>
3794 <bitfield name="UNK16" low="16" high="26"/>
3798 <!-- weird to duplicate other regs from same block?? -->
3800 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3801 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3805 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
3808 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
3810 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3811 <bitfield name="FLAGS" pos="2" type="boolean"/>
3812 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
3813 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
3814 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
3815 <bitfield name="UNK15" pos="15" type="boolean"/>
3816 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3820 <!-- array-pitch is size of layer -->
3824 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3825 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
3833 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
3835 …<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color rest…
3836 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
3837 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
3838 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
3841 1 - depth
3842 2 - stencil
3843 3 - depth+stencil
3847 <bitfield name="CLEAR_MASK" low="4" high="7"/>
3848 <!-- set when this is the last resolve on a650+ -->
3849 <bitfield name="LAST" low="8" high="9"/>
3850 <!--
3855 -->
3856 <bitfield name="BUFFER_ID" low="12" high="15"/>
3858 <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
3859 <!-- Value conditioned based on predicate, changed before blits -->
3860 <bitfield name="UNK0" pos="0" type="boolean"/>
3869 <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
3870 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
3871 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
3872 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
3873 <!-- GMEM offset of CCU depth cache -->
3874 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
3875 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
3876 <!-- GMEM offset of CCU color cache
3881 -->
3882 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
3884 <!-- 0x88e6-0x88ef invalid -->
3885 <!-- always 0x0 ? -->
3887 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
3890 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3891 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
3894 <!-- Connected to VK_EXT_fragment_density_map? -->
3895 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
3896 <!-- 0x88f6-0x88ff invalid -->
3899 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
3900 <!-- TODO: actually part of array pitch -->
3901 <bitfield name="UNK8" low="8" high="10"/>
3902 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
3907 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3908 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
3911 <!-- 0x891b-0x8926 invalid -->
3917 <!-- 0x8929-0x89ff invalid -->
3919 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
3921 <!--
3923 blob writing non-zero:
3924 -->
3934 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3935 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3936 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
3937 <bitfield name="FLAGS" pos="12" type="boolean"/>
3938 <bitfield name="SRGB" pos="13" type="boolean"/>
3939 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
3940 <bitfield name="FILTER" pos="16" type="boolean"/>
3941 <bitfield name="UNK17" pos="17" type="boolean"/>
3942 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
3943 <bitfield name="UNK19" pos="19" type="boolean"/>
3944 <bitfield name="UNK20" pos="20" type="boolean"/>
3945 <bitfield name="UNK21" pos="21" type="boolean"/>
3946 <bitfield name="UNK22" pos="22" type="boolean"/>
3947 <bitfield name="UNK23" low="23" high="26"/>
3948 <bitfield name="UNK28" pos="28" type="boolean"/>
3949 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/>
3953 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3954 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3955 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
3956 <bitfield name="FLAGS" pos="12" type="boolean"/>
3957 <bitfield name="SRGB" pos="13" type="boolean"/>
3958 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
3959 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/>
3962 <!-- 0x8c02-0x8c16 invalid -->
3966 <!-- this is a guess but seems likely (for NV12/IYUV): -->
3973 <!-- this is a guess but seems likely (for NV12 with UBWC): -->
3977 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
3978 <!-- unlike a5xx, these are per channel values rather than packed -->
3984 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
3986 <!-- 0x8c35-0x8dff invalid -->
3988 <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
3990 <!-- 0x8e00-0x8e03 invalid -->
3991 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
3993 <!-- 0x02080000 in GMEM, zero otherwise? -->
3994 <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
3997 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
3998 <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
3999 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
4000 <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/>
4001 <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/>
4002 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
4003 <!-- GMEM offset of CCU depth cache -->
4004 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
4005 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
4006 <!-- GMEM offset of CCU color cache
4011 -->
4012 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
4013 <!--TODO: valid mask 0xfffffc1f -->
4015 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
4016 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
4017 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
4018 <!-- rest of the bits were moved to RB_CCU_CNTL2 -->
4021 <bitfield name="MODE" pos="0" type="boolean"/>
4022 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
4023 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
4024 <bitfield name="AMSBC" pos="4" type="boolean"/>
4025 <bitfield name="UPPER_BIT" pos="10" type="uint"/>
4026 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
4027 <bitfield name="UNK12" low="12" high="13"/>
4029 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
4030 <!-- 0x8e09-0x8e0f invalid -->
4033 <!-- 0x8e1d-0x8e1f invalid -->
4034 <!-- 0x8e20-0x8e25 more perfcntr sel? -->
4035 <!-- 0x8e26-0x8e27 invalid -->
4037 <!-- 0x8e29-0x8e2b invalid -->
4039 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
4042 <!-- 0x8e3e-0x8e4f invalid -->
4043 <!-- GMEM save/restore for preemption: -->
4045 <!-- address for GMEM save/restore? -->
4047 <!-- 0x8e53-0x8e7f invalid -->
4048 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
4049 <!-- 0x8e80-0x8e83 are valid -->
4050 <!-- 0x8e84-0x90ff invalid -->
4052 <!-- 0x9000-0x90ff invalid -->
4055 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
4059 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
4060 <!-- there can be up to 8 total clip/cull distance outputs,
4063 -->
4064 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
4065 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
4076 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
4077 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
4078 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
4090 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
4091 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
4092 <bitfield name="UNK2" pos="2" type="boolean"/>
4095 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4099 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
4100 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
4101 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean">
4107 </bitfield>
4108 <bitfield name="UNK3" pos="3" type="boolean"/>
4115 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
4116 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
4117 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
4118 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
4119 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
4120 <bitfield name="UNK18" pos="18"/>
4124 <bitfield name="ENABLE" pos="0" type="boolean"/>
4125 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
4127 Multi-position output lets the last geometry
4133 </bitfield>
4134 <bitfield name="VIEWS" low="2" high="6" type="uint"/>
4137 …<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" u…
4138 …<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" u…
4139 …<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usa…
4140 …<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage…
4156 <!-- 0x9109-0x91ff invalid -->
4166 <!-- always 0x0 -->
4171 <!-- one bit per varying component: -->
4176 <!--
4196 This field is auto-incremented when VPC_SO_PROG is
4198 -->
4199 <bitfield name="ADDR" low="0" high="7" type="hex"/>
4200 <!-- clear all A_EN and B_EN bits for all DWORD's -->
4201 <bitfield name="RESET" pos="16" type="boolean"/>
4203 <!-- special register, write multiple times to load SO program (not readable) -->
4205 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
4206 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
4207 <bitfield name="A_EN" pos="11" type="boolean"/>
4208 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
4209 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
4210 <bitfield name="B_EN" pos="23" type="boolean"/>
4224 <bitfield name="INVERT" pos="0" type="boolean"/>
4226 <!-- 0x9237-0x92ff invalid -->
4227 <!-- always 0x0 ? -->
4233 plus # of transform-feedback (streamout) varyings if using the
4236 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4237 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
4238 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
4239 <bitfield name="EXTRAPOS" low="24" high="27" type="uint">
4242 number of views minus one when multi-position
4245 </bitfield>
4252 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
4253 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
4254 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
4255 <bitfield name="VARYING" pos="16" type="boolean"/>
4256 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
4261 strictly required for multi-position output,
4263 views at once, but it can be used when multi-pos
4267 </bitfield>
4271 <!--
4273 -->
4274 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
4275 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
4276 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
4277 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
4278 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
4281 <bitfield name="DISABLE" pos="0" type="boolean"/>
4283 <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
4284 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4286 <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4287 <bitfield name="SIZE_GMEM" low="0" high="31"/>
4289 <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
4290 <bitfield name="BASE_GMEM" low="0" high="31"/>
4292 <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4293 <bitfield name="SIZE_GMEM" low="0" high="31"/>
4296 <!-- 0x9307-0x95ff invalid -->
4298 <!-- TODO: 0x9600-0x97ff range -->
4299 …set="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -…
4301 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
4304 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
4305 <!-- 0x960a-0x9623 invalid -->
4306 <!-- TODO: regs from 0x9624-0x963a -->
4307 <!-- 0x963b-0x97ff invalid -->
4311 <!-- always 0x0 ? -->
4313 <bitfield name="SIZE" low="0" high="10" type="uint"/>
4314 <bitfield name="UNK13" pos="13"/>
4318 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
4319 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
4328 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
4331 <!-- New in a6xx gen3+ -->
4333 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
4337 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
4339 <!-- 0x980b-0x983f invalid -->
4341 <!-- 0x9840 - 0x9842 are not readable -->
4343 <bitfield name="STATE_ID" low="0" high="7"/>
4347 <bitfield name="STATE_ID" low="0" high="7"/>
4351 <!-- I think only the low bit is actually used? -->
4352 <bitfield name="STATE_ID" low="16" high="23"/>
4353 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4356 <!--
4360 -->
4363 <!-- 0x9843-0x997f invalid -->
4366 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4368 <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
4369 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4373 <!-- which stream to send to GRAS -->
4374 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4375 <!-- discard primitives before rasterization -->
4376 <bitfield name="DISCARD" pos="2" type="boolean"/>
4378 <!-- VPC_RASTER_CNTL -->
4379 <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
4380 <!-- which stream to send to GRAS -->
4381 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4382 <!-- discard primitives before rasterization -->
4383 <bitfield name="DISCARD" pos="2" type="boolean"/>
4385 <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
4386 <!-- which stream to send to GRAS -->
4387 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4388 <!-- discard primitives before rasterization -->
4389 <bitfield name="DISCARD" pos="2" type="boolean"/>
4392 <!-- Both are a750+.
4394 -->
4395 <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
4396 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
4398 -->
4399 <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
4401 <!-- 0x9982-0x9aff invalid -->
4408 plus # of transform-feedback (streamout) varyings if using the
4411 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4412 <bitfield name="PSIZE" pos="8" type="boolean"/>
4413 <bitfield name="LAYER" pos="9" type="boolean"/>
4414 <bitfield name="VIEW" pos="10" type="boolean"/>
4415 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
4416 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
4417 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
4418 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
4423 <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
4431 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
4433 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
4437 <!-- mask of enabled views, doesn't exist on A630 -->
4439 <!-- 0x9b09-0x9bff invalid -->
4441 <!-- special register (but note first 8 bits can be written/read) -->
4442 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4443 <bitfield name="STATE_ID" low="8" high="15"/>
4445 <!-- 0x9c01-0x9dff invalid -->
4446 <!-- TODO: 0x9e00-0xa000 range incomplete -->
4453 …<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage…
4464 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
4466 <bitfield name="UNK0" low="0" high="15"/>
4467 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
4468 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
4475 <bitfield name="OVERRIDE" pos="0" type="boolean"/>
4478 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
4481 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
4483 <!-- always 0x0 -->
4487 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
4488 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
4491 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
4492 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
4493 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
4494 <!-- only used for VS in non-multi-position-output case -->
4495 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
4498 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
4502 patch within the HS->DS buffers. When a draw is
4507 </bitfield>
4508 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
4511 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
4512 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
4513 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
4514 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
4517 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
4520 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
4521 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
4524 <!--
4526 -->
4527 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
4531 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
4536 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
4537 <bitfield name="VERTEX" pos="0" type="boolean"/>
4538 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
4539 <bitfield name="INSTANCE" pos="1" type="boolean"/>
4551 <!-- IDX and byte OFFSET into VFD_FETCH -->
4552 <bitfield name="IDX" low="0" high="4" type="uint"/>
4553 <bitfield name="OFFSET" low="5" high="16"/>
4554 <bitfield name="INSTANCED" pos="17" type="boolean"/>
4555 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
4556 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
4557 <bitfield name="UNK30" pos="30" type="boolean"/>
4558 <bitfield name="FLOAT" pos="31" type="boolean"/>
4564 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
4565 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
4571 <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
4575 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
4577 <!--
4580 -->
4587 <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
4588 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
4589 <!--
4592 - used (half): 0-15 68-179 (cnt=128, max=179)
4593 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
4597 - used (merged): 0-191 (cnt=192, max=191)
4602 -->
4603 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
4604 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
4605 <!-- could it be a low bit of branchstack? -->
4606 <bitfield name="UNK13" pos="13" type="boolean"/>
4607 <!-- seems to be nesting level for flow control:.. -->
4608 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
4612 <!--
4615 -->
4616 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
4617 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
4618 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
4619 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
4621 <bitfield name="ENABLED" pos="8" type="boolean"/>
4622 <!--
4625 -->
4626 <bitfield name="NTEX" low="9" high="16" type="uint"/>
4627 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
4628 <bitfield name="NIBO" low="22" high="28" type="uint"/>
4632 <!-- # of VS outputs including pos/psize -->
4633 <bitfield name="OUT" low="0" high="5" type="uint"/>
4634 <!-- FLAGS_REGID only for GS -->
4635 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
4639 <!--
4642 -->
4643 <bitfield name="MERGEDREGS" pos="20" type="boolean"/>
4644 <!--
4645 Creates a separate preamble-only thread?
4648 - Only shared, a1, and consts regs could be used
4650 - No cat5/cat6, only stc/ldc variants are working;
4651 - Values writen to shared regs are not accessible by the rest
4653 - Instructions before shps are also considered to be a part of
4658 -->
4659 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/>
4661 <!-- bitmask of true/false conditions for VS brac.N instructions,
4662 bit N corresponds to brac.N -->
4664 <!-- # of VS outputs including pos/psize -->
4668 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4669 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4670 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4671 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4674 <!--
4680 -->
4683 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4684 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4685 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4686 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4691 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
4693 </bitfield>
4694 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
4704 </bitfield>
4708 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
4709 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
4714 - stp/ldp offset
4715 - fiber id
4716 - wavefront id (a swizzled version of what "getwid" returns)
4717 - SP ID (the same as what "getspid" returns)
4720 TOTALPVTMEMSIZE. In the per-wave layout, the
4723 - offset % 4 (offset within dword)
4724 - fiber id
4725 - offset / 4
4726 - wavefront id
4727 - SP ID
4731 wavefront). In the per-fiber layout, the indices
4734 - offset
4735 - fiber id % 4
4736 - wavefront id
4737 - fiber id / 4
4738 - SP ID
4744 with per-fiber layout. The blob will fall back
4745 to per-wave instead.
4747 </bitfield>
4755 stack seems to be after all the normal per-SP private
4758 <bitfield name="OFFSET" low="0" high="18" shr="11"/>
4770 <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4773 <!-- There is no mergedregs bit, that comes from the VS. -->
4774 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
4776 <!--
4781 -->
4785 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4795 <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4798 <!-- There is no mergedregs bit, that comes from the VS. -->
4799 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
4803 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4807 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4808 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4809 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4810 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4815 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4816 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4817 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4818 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4822 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4832 <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4835 <!-- There is no mergedregs bit, that comes from the VS. -->
4836 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
4843 size less than 63 - size
4844 size of 63 (?) or 64 - 63
4845 size greater than 64 - 64
4847 What to program when the size is 61-63 is a guess, but
4854 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4858 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4859 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4860 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4861 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4867 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4868 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4869 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4870 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4874 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4884 <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4895 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
4898 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
4899 <bitfield name="UNK21" pos="21" type="boolean"/>
4900 <bitfield name="VARYING" pos="22" type="boolean"/>
4901 <bitfield name="LODPIXMASK" pos="23" type="boolean">
4906 </bitfield>
4907 <!-- note: vk blob uses bit24 -->
4908 <bitfield name="UNK24" pos="24" type="boolean"/>
4909 <bitfield name="UNK25" pos="25" type="boolean"/>
4910 <bitfield name="PIXLODENABLE" pos="26" type="boolean">
4916 </bitfield>
4917 <bitfield name="UNK27" pos="27" type="boolean"/>
4918 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/>
4919 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
4929 <!-- per-mrt enable bit -->
4930 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
4931 <bitfield name="UNK8" pos="8" type="boolean"/>
4932 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
4933 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
4936 <!-- Same as RB_SRGB_CNTL -->
4937 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
4938 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
4939 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
4940 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
4941 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
4942 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
4943 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
4944 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
4947 <bitfield name="RT0" low="0" high="3"/>
4948 <bitfield name="RT1" low="4" high="7"/>
4949 <bitfield name="RT2" low="8" high="11"/>
4950 <bitfield name="RT3" low="12" high="15"/>
4951 <bitfield name="RT4" low="16" high="19"/>
4952 <bitfield name="RT5" low="20" high="23"/>
4953 <bitfield name="RT6" low="24" high="27"/>
4954 <bitfield name="RT7" low="28" high="31"/>
4957 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
4958 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
4959 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
4960 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
4963 <bitfield name="MRT" low="0" high="3" type="uint"/>
4969 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
4970 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
4976 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
4977 <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
4978 <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
4979 <bitfield name="UNK10" pos="10" type="boolean"/>
4984 <bitfield name="COUNT" low="0" high="2" type="uint"/>
4985 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>
4990 <bitfield name="ENDOFQUAD" pos="4" type="boolean" />
4995 <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>
4996 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
4997 <!-- Blob never uses it -->
4998 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
5002 <bitfield name="SRC" low="0" high="6" type="uint"/>
5003 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
5004 <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
5005 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
5006 <bitfield name="WRMASK" low="22" high="25" type="hex"/>
5007 <bitfield name="HALF" pos="26" type="boolean"/>
5009 <bitfield name="UNK27" pos="27" type="boolean"/>
5010 <bitfield name="BINDLESS" pos="28" type="boolean"/>
5011 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>
5014 …<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit…
5015 <reg32 offset="0" name="CMD" variants="A7XX-">
5016 <bitfield name="SRC" low="0" high="6" type="uint"/>
5017 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/>
5018 <bitfield name="TEX_ID" low="10" high="12" type="uint"/>
5019 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/>
5020 <bitfield name="WRMASK" low="19" high="22" type="hex"/>
5021 <bitfield name="HALF" pos="23" type="boolean"/>
5022 <bitfield name="BINDLESS" pos="25" type="boolean"/>
5023 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>
5028 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
5029 <bitfield name="TEX_ID" low="16" high="31" type="uint"/>
5033 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
5036 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
5042 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
5043 <!-- seems to make SP use less concurrent threads when possible? -->
5044 <bitfield name="UNK21" pos="21" type="boolean"/>
5045 <!-- has a small impact on performance, not clear what it does -->
5046 <bitfield name="UNK22" pos="22" type="boolean"/>
5047 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/>
5048 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
5051 <!-- set for compute shaders -->
5053 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
5055 If 0 - all 32k of shared storage is enabled, otherwise
5059 64k (and has 36k of storage on A640 - reads between 36k-64k
5062 </bitfield>
5063 <bitfield name="UNK5" pos="5" type="boolean"/>
5064 <!-- always 1 ? -->
5065 <bitfield name="UNK6" pos="6" type="boolean"/>
5077 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
5078 <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
5080 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
5082 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5083 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
5084 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
5085 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
5087 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
5089 <!-- gl_LocalInvocationIndex -->
5090 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5091 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5092 one of those 6 "SP cores" -->
5093 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
5094 <!-- Must match SP_CS_CTRL -->
5095 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
5096 <!-- 1 thread per wave (ignored if bit9 set) -->
5097 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
5100 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
5101 <!-- gl_LocalInvocationIndex -->
5102 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5103 <!-- Must match SP_CS_CTRL -->
5104 <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/>
5105 <!-- 1 thread per wave (would hang if THREAD128 is also set) -->
5106 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/>
5108 <!-- Affects getone. If enabled, getone sometimes executed 1? less times
5110 -->
5111 <bitfield name="UNK15" pos="15" type="boolean"/>
5114 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
5132 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5133 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5136 …<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cm…
5137 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5138 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5139 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5143 <!--
5145 -->
5149 <!-- Correlated with avgs/uvgs usage in FS -->
5150 <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
5152 <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
5153 <bitfield name="ENABLED" pos="0" type="boolean"/>
5155 <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
5168 <bitfield name="RT0" low="0" high="3"/>
5169 <bitfield name="RT1" low="4" high="7"/>
5170 <bitfield name="RT2" low="8" high="11"/>
5171 <bitfield name="RT3" low="12" high="15"/>
5172 <bitfield name="RT4" low="16" high="19"/>
5173 <bitfield name="RT5" low="20" high="23"/>
5174 <bitfield name="RT6" low="24" high="27"/>
5175 <bitfield name="RT7" low="28" high="31"/>
5180 <!--
5183 out-of-bounds isam/isamm. GL and Vulkan robustness require us to
5184 return 0 on out-of-bound textureFetch().
5185 -->
5192 <!--
5194 load a 32-bit value (so hc0.y loads the same value as c0.y)
5199 -->
5200 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
5201 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
5202 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
5205 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
5206 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
5213 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5214 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5217 …<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_bl…
5218 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5219 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5220 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5224 <!--
5227 -->
5231 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
5234 <bitfield name="NORM" pos="0" type="boolean"/>
5235 <bitfield name="SINT" pos="1" type="boolean"/>
5236 <bitfield name="UINT" pos="2" type="boolean"/>
5237 <!-- looks like HW only cares about the base type of this format,
5238 which matches the ifmt? -->
5239 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
5240 <!-- set when ifmt is R2D_UNORM8_SRGB -->
5241 <bitfield name="SRGB" pos="11" type="boolean"/>
5242 <!-- some sort of channel mask, not sure what it is for -->
5243 <bitfield name="MASK" low="12" high="15"/>
5247 …<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage…
5252 <!-- TODO: valid bits 0x3c3f, see kernel -->
5256 <bitfield name="F16_NO_INF" pos="3" type="boolean"/>
5259 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
5260 <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
5261 <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
5262 <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
5265 <!-- some perfcntrs are affected by a per-stage enable bit
5267 TODO: verify position of HS/DS/GS bits -->
5268 <bitfield name="VS" pos="0" type="boolean"/>
5269 <bitfield name="HS" pos="1" type="boolean"/>
5270 <bitfield name="DS" pos="2" type="boolean"/>
5271 <bitfield name="GS" pos="3" type="boolean"/>
5272 <bitfield name="FS" pos="4" type="boolean"/>
5273 <bitfield name="CS" pos="5" type="boolean"/>
5276 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
5277 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
5278 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
5279 <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
5280 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
5281 <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>
5282 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
5283 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
5284 <bitfield name="USPTP" low="4" high="7"/>
5285 <bitfield name="SPTP" low="0" high="3"/>
5287 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
5288 <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
5289 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
5290 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
5291 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
5294 <!--
5298 -->
5306 <!-- could be all the stuff below here is actually TPL1?? -->
5309 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5310 <bitfield name="UNK2" low="2" high="3"/>
5313 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5314 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
5317 <!-- looks to work in the same way as a5xx: -->
5324 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
5325 <bitfield name="UNK3" low="2" high="7"/>
5327 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
5329 <!--
5333 -->
5336 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5337 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5341 <bitfield name="UNK0" low="0" high="8"/>
5342 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
5345 …<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usag…
5347 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5348 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5350 …<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_bl…
5352 <bitfield name="UNK0" low="0" high="8"/>
5353 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
5356 <!-- planes for NV12, etc. (TODO: not tested) -->
5361 <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
5362 …t="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>
5363 <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
5368 …<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage=…
5369 …="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>
5382 <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
5383 …<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"…
5385 <!-- always 0x100000 or 0x1000000? -->
5389 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set
5390 and if other blit is done without it - UBWC image may be copied incorrectly.
5391 -->
5392 <bitfield name="TP_UBWC_FLAG_HINT" pos="18" type="boolean"/>
5395 <bitfield name="MODE" pos="0" type="boolean"/>
5396 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
5397 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
5398 <bitfield name="UPPER_BIT" pos="4" type="uint"/>
5399 <bitfield name="UNK6" low="6" high="7"/>
5401 …NOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
5418 <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
5421 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
5422 <bitfield name="ENABLED" pos="8" type="boolean"/>
5423 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
5431 …<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5432 …<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5433 …<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5434 …<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5436 <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
5437 <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
5438 <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
5441 <!-- Always 0 -->
5442 <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
5444 <!-- Used in VK_KHR_fragment_shading_rate -->
5445 <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
5447 <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
5448 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
5449 <!-- UNK8 is set on a730/a740 -->
5450 <bitfield name="UNK8" pos="8" type="boolean"/>
5451 <!-- UNK9 is set on a750 -->
5452 <bitfield name="UNK9" pos="9" type="boolean"/>
5461 <!-- must match SP_FS_CTRL -->
5462 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
5463 <bitfield name="VARYINGS" pos="1" type="boolean"/>
5464 <bitfield name="UNK2" low="2" high="11"/>
5467 <!-- register loaded with position (bary.f) -->
5468 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
5469 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
5470 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
5471 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
5474 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
5475 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
5476 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
5477 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
5480 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
5481 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
5485 …b981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
5487 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
5489 the hardware will simply emit smaller waves when it runs out of space. -->
5490 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5493 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5494 <!-- SAMPLEID is loaded into a half-precision register: -->
5495 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
5496 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
5497 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
5503 …<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp…
5504 <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
5505 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5507 <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
5508 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5509 <!-- SAMPLEID is loaded into a half-precision register: -->
5510 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
5511 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
5512 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
5514 …<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" u…
5515 …<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" u…
5516 …<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" u…
5517 <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
5519 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5521 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5522 <!-- localsize is value minus one: -->
5523 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5524 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5525 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5528 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5531 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5534 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5537 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5540 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5543 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5546 <!-- these are all vec3. first 3 need to be high regs
5549 -->
5550 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5551 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
5552 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
5553 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
5556 <!-- gl_LocalInvocationIndex -->
5557 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5558 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5559 one of those 6 "SP cores" -->
5560 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
5561 <!-- Must match SP_CS_CTRL -->
5562 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
5563 <!-- 1 thread per wave (ignored if bit9 set) -->
5564 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
5566 <!--note: vulkan blob doesn't use these -->
5571 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5572 <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
5573 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5574 <!-- localsize is value minus one: -->
5575 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5576 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5577 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5579 <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
5580 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5582 <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
5583 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5585 <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
5586 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5588 <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
5589 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5591 <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
5592 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5594 <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
5595 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5597 <!--note: vulkan blob doesn't use these -->
5598 <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
5599 <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
5600 <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
5609 <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
5610 <!-- gl_LocalInvocationIndex -->
5611 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5612 <!-- Must match SP_CS_CTRL -->
5613 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
5614 <bitfield name="UNK11" pos="11" type="boolean"/>
5615 <bitfield name="UNK22" pos="22" type="boolean"/>
5616 <bitfield name="UNK26" pos="26" type="boolean"/>
5617 <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>
5620 <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
5621 <!-- localsize is value minus one: -->
5622 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5623 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5624 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5631 <!-- mirror of SP_CS_BINDLESS_BASE -->
5634 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5635 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5639 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
5641 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
5642 <bitfield name="UNK5" pos="5" type="boolean"/>
5643 <!-- always 1 ? -->
5644 <bitfield name="UNK6" pos="6" type="boolean"/>
5648 <bitfield name="STATE_ID" low="0" high="7"/>
5652 <bitfield name="STATE_ID" low="0" high="7"/>
5656 <!-- I think only the low bit is actually used? -->
5657 <bitfield name="STATE_ID" low="16" high="23"/>
5658 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5668 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5669 <bitfield name="VS_STATE" pos="0" type="boolean"/>
5670 <bitfield name="HS_STATE" pos="1" type="boolean"/>
5671 <bitfield name="DS_STATE" pos="2" type="boolean"/>
5672 <bitfield name="GS_STATE" pos="3" type="boolean"/>
5673 <bitfield name="FS_STATE" pos="4" type="boolean"/>
5674 <bitfield name="CS_STATE" pos="5" type="boolean"/>
5676 <bitfield name="CS_IBO" pos="6" type="boolean"/>
5677 <bitfield name="GFX_IBO" pos="7" type="boolean"/>
5679 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
5680 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
5681 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
5683 <!-- SS6_BINDLESS: one bit per bindless base -->
5684 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
5685 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
5688 <reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">
5689 <bitfield name="STATE_ID" low="0" high="7"/>
5692 <reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">
5693 <bitfield name="STATE_ID" low="0" high="7"/>
5696 <reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">
5697 <bitfield name="STATE_ID" low="16" high="23"/>
5698 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5701 <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
5708 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5709 <bitfield name="VS_STATE" pos="0" type="boolean"/>
5710 <bitfield name="HS_STATE" pos="1" type="boolean"/>
5711 <bitfield name="DS_STATE" pos="2" type="boolean"/>
5712 <bitfield name="GS_STATE" pos="3" type="boolean"/>
5713 <bitfield name="FS_STATE" pos="4" type="boolean"/>
5714 <bitfield name="CS_STATE" pos="5" type="boolean"/>
5716 <bitfield name="CS_IBO" pos="6" type="boolean"/>
5717 <bitfield name="GFX_IBO" pos="7" type="boolean"/>
5719 <!-- SS6_BINDLESS: one bit per bindless base -->
5720 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
5721 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
5725 …<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5727 <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
5735 c504-c511 in each stage. Both VS and FS shared consts
5748 <bitfield name="ENABLE" pos="0" type="boolean"/>
5751 <!-- mirror of SP_BINDLESS_BASE -->
5754 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5755 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5760 <bitfield name="STATE_ID" low="8" high="15"/>
5761 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5764 …xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
5771 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
5774 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
5776 <!-- Don't know if these are SP, always 0 -->
5777 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
5778 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
5779 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
5781 <!--
5784 - write EVENT_CMD pipe register
5785 - write CP_EVENT_START
5786 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
5787 - write PC_EVENT_CMD with event or PC_DRAW_CMD
5788 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
5789 - write PC_EVENT_CMD(CONTEXT_DONE)
5790 - write CP_EVENT_END
5792 -->
5794 <bitfield name="STATE_ID" low="0" high="7"/>
5797 <bitfield name="STATE_ID" low="0" high="7"/>
5800 <bitfield name="STATE_ID" low="0" high="7"/>
5803 <bitfield name="STATE_ID" low="0" high="7"/>
5807 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
5808 <domain name="A6XX_TEX_SAMP" width="32">
5810 <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
5814 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
5816 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
5823 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
5837 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
5838 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
5839 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
5840 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
5841 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
5842 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
5843 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
5844 …<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits fo…
5847 <bitfield name="CLAMPENABLE" pos="0" type="boolean">
5850 [-1, 1] if the format is snorm, *after*
5853 </bitfield>
5854 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
5855 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
5856 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
5857 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
5858 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
5859 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
5862 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
5863 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
5864 <bitfield name="BCOLOR" low="7" high="31"/>
5869 <domain name="A6XX_TEX_CONST" width="32" varset="chip">
5871 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
5879 <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
5887 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
5888 <bitfield name="SRGB" pos="2" type="boolean"/>
5889 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
5890 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
5891 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
5892 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
5893 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
5894 <!-- overlaps with MIPLVLS -->
5895 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
5896 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
5897 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
5898 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
5899 <!--
5903 -->
5904 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
5907 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5908 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5909 <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>
5912 <!--
5915 -->
5917 <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
5918 <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
5920 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
5921 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
5923 <bitfield name="PITCH" low="7" high="28" type="uint"/>
5924 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
5927 <!--
5932 -->
5933 <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
5934 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
5935 <!--
5939 -->
5940 <bitfield name="TILE_ALL" pos="27" type="boolean"/>
5941 <bitfield name="FLAG" pos="28" type="boolean"/>
5943 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
5944 the address of the non-flag base buffer is determined automatically,
5946 -->
5948 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
5951 <bitfield name="BASE_HI" low="0" high="16"/>
5952 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
5955 <!-- overlaps with PLANE_PITCH -->
5956 <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
5957 <!-- pitch for plane 2 / plane 3 -->
5958 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
5960 <!-- 7/8 is plane 2 address for planar formats -->
5962 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
5965 <bitfield name="FLAG_HI" low="0" high="16"/>
5967 <!-- 9/10 is plane 3 address for planar formats -->
5969 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
5972 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
5973 <!-- log2 size of the first level, required for mipmapping -->
5974 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
5975 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
5984 <domain name="A6XX_UBO" width="32">
5986 <bitfield name="BASE_LO" low="0" high="31"/>
5989 <bitfield name="BASE_HI" low="0" high="16"/>
5990 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
5994 <domain name="A6XX_PDC" width="32">
6023 <domain name="A6XX_PDC_GPU_SEQ" width="32">
6027 <domain name="A6XX_CX_DBGC" width="32">
6029 <bitfield high="7" low="0" name="PING_INDEX"/>
6030 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
6036 <bitfield high="5" low="0" name="TRACEEN"/>
6037 <bitfield high="14" low="12" name="GRANU"/>
6038 <bitfield high="31" low="28" name="SEGT"/>
6041 <bitfield high="27" low="24" name="ENABLE"/>
6052 <bitfield high="3" low="0" name="BYTEL0"/>
6053 <bitfield high="7" low="4" name="BYTEL1"/>
6054 <bitfield high="11" low="8" name="BYTEL2"/>
6055 <bitfield high="15" low="12" name="BYTEL3"/>
6056 <bitfield high="19" low="16" name="BYTEL4"/>
6057 <bitfield high="23" low="20" name="BYTEL5"/>
6058 <bitfield high="27" low="24" name="BYTEL6"/>
6059 <bitfield high="31" low="28" name="BYTEL7"/>
6062 <bitfield high="3" low="0" name="BYTEL8"/>
6063 <bitfield high="7" low="4" name="BYTEL9"/>
6064 <bitfield high="11" low="8" name="BYTEL10"/>
6065 <bitfield high="15" low="12" name="BYTEL11"/>
6066 <bitfield high="19" low="16" name="BYTEL12"/>
6067 <bitfield high="23" low="20" name="BYTEL13"/>
6068 <bitfield high="27" low="24" name="BYTEL14"/>
6069 <bitfield high="31" low="28" name="BYTEL15"/>
6076 <domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
6079 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
6080 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
6081 <bitfield pos="0" name="FASTBLEND" type="boolean"/>
6082 <bitfield pos="1" name="LPAC" type="boolean"/>
6083 <bitfield pos="2" name="RAYTRACING" type="boolean"/>