Lines Matching +full:0 +full:x209c
10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
21 <value name="RB4_R8G8_UINT" value="0x11"/>
22 <value name="RB4_R8G8_SINT" value="0x12"/>
23 <value name="RB4_R16_UNORM" value="0x13"/>
24 <value name="RB4_R16_SNORM" value="0x14"/>
25 <value name="RB4_R16_FLOAT" value="0x15"/>
26 <value name="RB4_R16_UINT" value="0x16"/>
27 <value name="RB4_R16_SINT" value="0x17"/>
29 <value name="RB4_R8G8B8_UNORM" value="0x19"/>
31 <value name="RB4_R8G8B8A8_UNORM" value="0x1a"/>
32 <value name="RB4_R8G8B8A8_SNORM" value="0x1c"/>
33 <value name="RB4_R8G8B8A8_UINT" value="0x1d"/>
34 <value name="RB4_R8G8B8A8_SINT" value="0x1e"/>
35 <value name="RB4_R10G10B10A2_UNORM" value="0x1f"/>
36 <value name="RB4_R10G10B10A2_UINT" value="0x22"/>
37 <value name="RB4_R11G11B10_FLOAT" value="0x27"/>
38 <value name="RB4_R16G16_UNORM" value="0x28"/>
39 <value name="RB4_R16G16_SNORM" value="0x29"/>
40 <value name="RB4_R16G16_FLOAT" value="0x2a"/>
41 <value name="RB4_R16G16_UINT" value="0x2b"/>
42 <value name="RB4_R16G16_SINT" value="0x2c"/>
43 <value name="RB4_R32_FLOAT" value="0x2d"/>
44 <value name="RB4_R32_UINT" value="0x2e"/>
45 <value name="RB4_R32_SINT" value="0x2f"/>
47 <value name="RB4_R16G16B16A16_UNORM" value="0x34"/>
48 <value name="RB4_R16G16B16A16_SNORM" value="0x35"/>
49 <value name="RB4_R16G16B16A16_FLOAT" value="0x36"/>
50 <value name="RB4_R16G16B16A16_UINT" value="0x37"/>
51 <value name="RB4_R16G16B16A16_SINT" value="0x38"/>
52 <value name="RB4_R32G32_FLOAT" value="0x39"/>
53 <value name="RB4_R32G32_UINT" value="0x3a"/>
54 <value name="RB4_R32G32_SINT" value="0x3b"/>
56 <value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/>
57 <value name="RB4_R32G32B32A32_UINT" value="0x3d"/>
58 <value name="RB4_R32G32B32A32_SINT" value="0x3e"/>
60 <value name="RB4_NONE" value="0xff"/>
64 <value name="TILE4_LINEAR" value="0"/>
71 <value name="VFMT4_32_FLOAT" value="0x1"/>
72 <value name="VFMT4_32_32_FLOAT" value="0x2"/>
73 <value name="VFMT4_32_32_32_FLOAT" value="0x3"/>
74 <value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/>
76 <value name="VFMT4_16_FLOAT" value="0x5"/>
77 <value name="VFMT4_16_16_FLOAT" value="0x6"/>
78 <value name="VFMT4_16_16_16_FLOAT" value="0x7"/>
79 <value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/>
81 <value name="VFMT4_32_FIXED" value="0x9"/>
82 <value name="VFMT4_32_32_FIXED" value="0xa"/>
83 <value name="VFMT4_32_32_32_FIXED" value="0xb"/>
84 <value name="VFMT4_32_32_32_32_FIXED" value="0xc"/>
86 <value name="VFMT4_11_11_10_FLOAT" value="0xd"/>
89 <value name="VFMT4_16_SINT" value="0x10"/>
90 <value name="VFMT4_16_16_SINT" value="0x11"/>
91 <value name="VFMT4_16_16_16_SINT" value="0x12"/>
92 <value name="VFMT4_16_16_16_16_SINT" value="0x13"/>
93 <value name="VFMT4_16_UINT" value="0x14"/>
94 <value name="VFMT4_16_16_UINT" value="0x15"/>
95 <value name="VFMT4_16_16_16_UINT" value="0x16"/>
96 <value name="VFMT4_16_16_16_16_UINT" value="0x17"/>
97 <value name="VFMT4_16_SNORM" value="0x18"/>
98 <value name="VFMT4_16_16_SNORM" value="0x19"/>
99 <value name="VFMT4_16_16_16_SNORM" value="0x1a"/>
100 <value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/>
101 <value name="VFMT4_16_UNORM" value="0x1c"/>
102 <value name="VFMT4_16_16_UNORM" value="0x1d"/>
103 <value name="VFMT4_16_16_16_UNORM" value="0x1e"/>
104 <value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/>
106 <value name="VFMT4_32_UINT" value="0x20"/>
107 <value name="VFMT4_32_32_UINT" value="0x21"/>
108 <value name="VFMT4_32_32_32_UINT" value="0x22"/>
109 <value name="VFMT4_32_32_32_32_UINT" value="0x23"/>
110 <value name="VFMT4_32_SINT" value="0x24"/>
111 <value name="VFMT4_32_32_SINT" value="0x25"/>
112 <value name="VFMT4_32_32_32_SINT" value="0x26"/>
113 <value name="VFMT4_32_32_32_32_SINT" value="0x27"/>
115 <value name="VFMT4_8_UINT" value="0x28"/>
116 <value name="VFMT4_8_8_UINT" value="0x29"/>
117 <value name="VFMT4_8_8_8_UINT" value="0x2a"/>
118 <value name="VFMT4_8_8_8_8_UINT" value="0x2b"/>
119 <value name="VFMT4_8_UNORM" value="0x2c"/>
120 <value name="VFMT4_8_8_UNORM" value="0x2d"/>
121 <value name="VFMT4_8_8_8_UNORM" value="0x2e"/>
122 <value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/>
123 <value name="VFMT4_8_SINT" value="0x30"/>
124 <value name="VFMT4_8_8_SINT" value="0x31"/>
125 <value name="VFMT4_8_8_8_SINT" value="0x32"/>
126 <value name="VFMT4_8_8_8_8_SINT" value="0x33"/>
127 <value name="VFMT4_8_SNORM" value="0x34"/>
128 <value name="VFMT4_8_8_SNORM" value="0x35"/>
129 <value name="VFMT4_8_8_8_SNORM" value="0x36"/>
130 <value name="VFMT4_8_8_8_8_SNORM" value="0x37"/>
132 <value name="VFMT4_10_10_10_2_UINT" value="0x38"/>
133 <value name="VFMT4_10_10_10_2_UNORM" value="0x39"/>
134 <value name="VFMT4_10_10_10_2_SINT" value="0x3a"/>
135 <value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/>
136 <value name="VFMT4_2_10_10_10_UINT" value="0x3c"/>
137 <value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/>
138 <value name="VFMT4_2_10_10_10_SINT" value="0x3e"/>
139 <value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/>
141 <value name="VFMT4_NONE" value="0xff"/>
145 <!-- 0x00 .. 0x02 -->
148 <value name="TFMT4_A8_UNORM" value="0x03"/>
149 <value name="TFMT4_8_UNORM" value="0x04"/>
150 <value name="TFMT4_8_SNORM" value="0x05"/>
151 <value name="TFMT4_8_UINT" value="0x06"/>
152 <value name="TFMT4_8_SINT" value="0x07"/>
155 <value name="TFMT4_4_4_4_4_UNORM" value="0x08"/>
156 <value name="TFMT4_5_5_5_1_UNORM" value="0x09"/>
157 <!-- 0x0a -->
158 <value name="TFMT4_5_6_5_UNORM" value="0x0b"/>
160 <!-- 0x0c -->
162 <value name="TFMT4_L8_A8_UNORM" value="0x0d"/>
163 <value name="TFMT4_8_8_UNORM" value="0x0e"/>
164 <value name="TFMT4_8_8_SNORM" value="0x0f"/>
165 <value name="TFMT4_8_8_UINT" value="0x10"/>
166 <value name="TFMT4_8_8_SINT" value="0x11"/>
168 <value name="TFMT4_16_UNORM" value="0x12"/>
169 <value name="TFMT4_16_SNORM" value="0x13"/>
170 <value name="TFMT4_16_FLOAT" value="0x14"/>
171 <value name="TFMT4_16_UINT" value="0x15"/>
172 <value name="TFMT4_16_SINT" value="0x16"/>
174 <!-- 0x17 .. 0x1b -->
177 <value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/>
178 <value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/>
179 <value name="TFMT4_8_8_8_8_UINT" value="0x1e"/>
180 <value name="TFMT4_8_8_8_8_SINT" value="0x1f"/>
182 <value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/>
183 <value name="TFMT4_10_10_10_2_UNORM" value="0x21"/>
184 <value name="TFMT4_10_10_10_2_UINT" value="0x22"/>
185 <!-- 0x23 .. 0x24 -->
186 <value name="TFMT4_11_11_10_FLOAT" value="0x25"/>
188 <value name="TFMT4_16_16_UNORM" value="0x26"/>
189 <value name="TFMT4_16_16_SNORM" value="0x27"/>
190 <value name="TFMT4_16_16_FLOAT" value="0x28"/>
191 <value name="TFMT4_16_16_UINT" value="0x29"/>
192 <value name="TFMT4_16_16_SINT" value="0x2a"/>
194 <value name="TFMT4_32_FLOAT" value="0x2b"/>
195 <value name="TFMT4_32_UINT" value="0x2c"/>
196 <value name="TFMT4_32_SINT" value="0x2d"/>
198 <!-- 0x2e .. 0x32 -->
201 <value name="TFMT4_16_16_16_16_UNORM" value="0x33"/>
202 <value name="TFMT4_16_16_16_16_SNORM" value="0x34"/>
203 <value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/>
204 <value name="TFMT4_16_16_16_16_UINT" value="0x36"/>
205 <value name="TFMT4_16_16_16_16_SINT" value="0x37"/>
207 <value name="TFMT4_32_32_FLOAT" value="0x38"/>
208 <value name="TFMT4_32_32_UINT" value="0x39"/>
209 <value name="TFMT4_32_32_SINT" value="0x3a"/>
212 <value name="TFMT4_32_32_32_FLOAT" value="0x3b"/>
213 <value name="TFMT4_32_32_32_UINT" value="0x3c"/>
214 <value name="TFMT4_32_32_32_SINT" value="0x3d"/>
216 <!-- 0x3e -->
219 <value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/>
220 <value name="TFMT4_32_32_32_32_UINT" value="0x40"/>
221 <value name="TFMT4_32_32_32_32_SINT" value="0x41"/>
223 <!-- 0x42 .. 0x46 -->
224 <value name="TFMT4_X8Z24_UNORM" value="0x47"/>
225 <!-- 0x48 .. 0x55 -->
228 <value name="TFMT4_DXT1" value="0x56"/>
229 <value name="TFMT4_DXT3" value="0x57"/>
230 <value name="TFMT4_DXT5" value="0x58"/>
231 <!-- 0x59 -->
232 <value name="TFMT4_RGTC1_UNORM" value="0x5a"/>
233 <value name="TFMT4_RGTC1_SNORM" value="0x5b"/>
234 <!-- 0x5c .. 0x5d -->
235 <value name="TFMT4_RGTC2_UNORM" value="0x5e"/>
236 <value name="TFMT4_RGTC2_SNORM" value="0x5f"/>
237 <!-- 0x60 -->
238 <value name="TFMT4_BPTC_UFLOAT" value="0x61"/>
239 <value name="TFMT4_BPTC_FLOAT" value="0x62"/>
240 <value name="TFMT4_BPTC" value="0x63"/>
241 <value name="TFMT4_ATC_RGB" value="0x64"/>
242 <value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/>
243 <value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/>
244 <value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/>
245 <value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/>
246 <value name="TFMT4_ETC2_R11_UNORM" value="0x69"/>
247 <value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/>
248 <value name="TFMT4_ETC1" value="0x6b"/>
249 <value name="TFMT4_ETC2_RGB8" value="0x6c"/>
250 <value name="TFMT4_ETC2_RGBA8" value="0x6d"/>
251 <value name="TFMT4_ETC2_RGB8A1" value="0x6e"/>
252 <value name="TFMT4_ASTC_4x4" value="0x6f"/>
253 <value name="TFMT4_ASTC_5x4" value="0x70"/>
254 <value name="TFMT4_ASTC_5x5" value="0x71"/>
255 <value name="TFMT4_ASTC_6x5" value="0x72"/>
256 <value name="TFMT4_ASTC_6x6" value="0x73"/>
257 <value name="TFMT4_ASTC_8x5" value="0x74"/>
258 <value name="TFMT4_ASTC_8x6" value="0x75"/>
259 <value name="TFMT4_ASTC_8x8" value="0x76"/>
260 <value name="TFMT4_ASTC_10x5" value="0x77"/>
261 <value name="TFMT4_ASTC_10x6" value="0x78"/>
262 <value name="TFMT4_ASTC_10x8" value="0x79"/>
263 <value name="TFMT4_ASTC_10x10" value="0x7a"/>
264 <value name="TFMT4_ASTC_12x10" value="0x7b"/>
265 <value name="TFMT4_ASTC_12x12" value="0x7c"/>
266 <!-- 0x7d .. 0x7f -->
268 <value name="TFMT4_NONE" value="0xff"/>
272 <value name="DEPTH4_NONE" value="0"/>
317 <value value="0" name="CCU_BUSY_CYCLES"/>
343 <value value="0" name="CP_ALWAYS_COUNT"/>
387 <value value="0" name="RAS_SUPER_TILES"/>
404 <value value="0" name="TSE_INPUT_PRIM"/>
424 <value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/>
452 <value value="0" name="PC_VIS_STREAMS_LOADED"/>
496 <value value="0" name="PWR_CORE_CLOCK_CYCLES"/>
501 <value value="0" name="RB_BUSY_CYCLES"/>
553 <value value="0" name="RBBM_ALWAYS_ON"/>
585 <value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/>
646 <value value="0" name="TP_L1_REQUESTS"/>
669 <value value="0" name="UCHE_VBIF_READ_BEATS_TP"/>
703 <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
818 <value value="0" name="VFD_UCHE_BYTE_FETCHED"/>
856 <value value="0" name="VSC_BUSY_CYCLES"/>
865 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866 <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867 <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868 <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869 <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870 <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871 <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872 <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873 <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874 <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
875 <reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/>
876 <reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/>
877 <reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/>
878 <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
879 <bitfield name="WIDTH" low="0" high="13" type="uint"/>
882 <reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/>
883 <reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/>
884 <reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/>
885 <reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/>
886 <reg32 offset="0x20a0" name="RB_MODE_CONTROL">
893 <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
897 <reg32 offset="0x20a1" name="RB_RENDER_CONTROL">
898 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
903 <reg32 offset="0x20a2" name="RB_MSAA_CONTROL">
907 <reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
908 <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
922 <array offset="0x20a4" name="RB_MRT" stride="5" length="8">
923 <reg32 offset="0x0" name="CONTROL">
932 <reg32 offset="0x1" name="BUF_INFO">
933 <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
949 <reg32 offset="0x2" name="BASE"/>
950 <reg32 offset="0x3" name="CONTROL3">
955 <reg32 offset="0x4" name="BLEND_CONTROL">
956 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
965 <reg32 offset="0x20f0" name="RB_BLEND_RED">
966 <bitfield name="UINT" low="0" high="7" type="hex"/>
970 <reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/>
972 <reg32 offset="0x20f2" name="RB_BLEND_GREEN">
973 <bitfield name="UINT" low="0" high="7" type="hex"/>
977 <reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/>
979 <reg32 offset="0x20f4" name="RB_BLEND_BLUE">
980 <bitfield name="UINT" low="0" high="7" type="hex"/>
984 <reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/>
986 <reg32 offset="0x20f6" name="RB_BLEND_ALPHA">
987 <bitfield name="UINT" low="0" high="7" type="hex"/>
991 <reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/>
993 <reg32 offset="0x20f8" name="RB_ALPHA_CONTROL">
994 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
998 <reg32 offset="0x20f9" name="RB_FS_OUTPUT">
1000 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
1005 <reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL">
1010 <reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS">
1011 <bitfield name="RT0" low="0" high="3"/>
1021 <reg32 offset="0x20fc" name="RB_COPY_CONTROL">
1023 <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
1028 <reg32 offset="0x20fd" name="RB_COPY_DEST_BASE">
1031 <reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH">
1034 <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
1036 <reg32 offset="0x20ff" name="RB_COPY_DEST_INFO">
1044 <reg32 offset="0x2100" name="RB_FS_OUTPUT_REG">
1046 <bitfield name="MRT" low="0" high="3" type="uint"/>
1049 <reg32 offset="0x2101" name="RB_DEPTH_CONTROL">
1054 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1064 <reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
1065 <reg32 offset="0x2103" name="RB_DEPTH_INFO">
1066 <bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1075 <reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint">
1078 <reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint">
1081 <reg32 offset="0x2106" name="RB_STENCIL_CONTROL">
1082 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1100 <reg32 offset="0x2107" name="RB_STENCIL_CONTROL2">
1107 <bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/>
1109 <reg32 offset="0x2108" name="RB_STENCIL_INFO">
1110 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
1114 <reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint">
1118 <reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1119 <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1120 <reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/>
1121 <array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16">
1122 <reg32 offset="0x0" name="MIN"/>
1123 <reg32 offset="0x1" name="MAX"/>
1127 <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
1128 <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
1129 <array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4">
1130 <reg32 offset="0x0" name="REG"/>
1132 <array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4">
1133 <reg32 offset="0x0" name="REG"/>
1135 <array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4">
1136 <reg32 offset="0x0" name="REG"/>
1138 <array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4">
1139 <reg32 offset="0x0" name="REG"/>
1141 <reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/>
1142 <reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/>
1143 <reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/>
1144 <reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/>
1145 <reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/>
1146 <reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/>
1147 <reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/>
1148 <reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/>
1149 <reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/>
1150 <reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/>
1151 <reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1152 <reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1153 <reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/>
1154 <reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/>
1155 <reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/>
1156 <reg32 offset="0x0023" name="RBBM_AHB_CTL0"/>
1157 <reg32 offset="0x0024" name="RBBM_AHB_CTL1"/>
1158 <reg32 offset="0x0025" name="RBBM_AHB_CMD"/>
1159 <reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/>
1160 <reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/>
1161 <reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
1162 <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/>
1163 <reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/>
1164 <reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/>
1165 <reg32 offset="0x0037" name="RBBM_INT_0_MASK"/>
1166 <reg32 offset="0x003e" name="RBBM_RBBM_CTL"/>
1167 <reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/>
1168 <reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/>
1169 <reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/>
1170 <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1171 <reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/>
1172 <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/>
1173 <reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/>
1174 <reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/>
1175 <reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/>
1176 <reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/>
1177 <reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP">
1178 <bitfield name="SW_COLLAPSE" pos="0" type="boolean"/>
1181 <reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/>
1182 <reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/>
1183 <reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/>
1184 <reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/>
1185 <reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/>
1186 <reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/>
1187 <reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/>
1188 <reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/>
1189 <reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/>
1190 <reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/>
1191 <reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/>
1192 <reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/>
1193 <reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/>
1194 <reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/>
1195 <reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/>
1196 <reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/>
1197 <reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/>
1198 <reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/>
1199 <reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/>
1200 <reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/>
1201 <reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/>
1202 <reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/>
1203 <reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/>
1204 <reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/>
1205 <reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/>
1206 <reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/>
1207 <reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/>
1208 <reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/>
1209 <reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/>
1210 <reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/>
1211 <reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/>
1212 <reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/>
1213 <reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/>
1214 <reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/>
1215 <reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/>
1216 <reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/>
1217 <reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/>
1218 <reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/>
1219 <reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/>
1220 <reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/>
1221 <reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/>
1222 <reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/>
1223 <reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/>
1224 <reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/>
1225 <reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/>
1226 <reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/>
1227 <reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/>
1228 <reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/>
1229 <reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/>
1230 <reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/>
1231 <reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/>
1232 <reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/>
1233 <reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/>
1234 <reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/>
1235 <reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/>
1236 <reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/>
1237 <reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1238 <reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1239 <reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1240 <reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1241 <reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1242 <reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1243 <reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1244 <reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1245 <reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1246 <reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1247 <reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1248 <reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1249 <reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1250 <reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1251 <reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1252 <reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1253 <reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/>
1254 <reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/>
1255 <reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/>
1256 <reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/>
1257 <reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/>
1258 <reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/>
1259 <reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/>
1260 <reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/>
1261 <reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/>
1262 <reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/>
1263 <reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/>
1264 <reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/>
1265 <reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/>
1266 <reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/>
1267 <reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/>
1268 <reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/>
1269 <reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/>
1270 <reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/>
1271 <reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/>
1272 <reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/>
1273 <reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/>
1274 <reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/>
1275 <reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/>
1276 <reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/>
1277 <reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/>
1278 <reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/>
1279 <reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/>
1280 <reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/>
1281 <reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/>
1282 <reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/>
1283 <reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/>
1284 <reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/>
1285 <reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/>
1286 <reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/>
1287 <reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/>
1288 <reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/>
1289 <reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/>
1290 <reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/>
1291 <reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/>
1292 <reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/>
1293 <reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/>
1294 <reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/>
1295 <reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/>
1296 <reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/>
1297 <reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/>
1298 <reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/>
1299 <reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/>
1300 <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
1301 <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
1302 <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
1303 <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
1304 <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
1305 <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
1306 <reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/>
1307 <reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/>
1308 <reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/>
1309 <reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/>
1310 <reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/>
1311 <reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/>
1312 <reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/>
1313 <reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/>
1314 <reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/>
1315 <reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/>
1316 <reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/>
1317 <reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/>
1318 <reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/>
1319 <reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/>
1320 <reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/>
1321 <reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/>
1322 <reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/>
1323 <reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/>
1324 <reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/>
1325 <reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/>
1326 <reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/>
1327 <reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/>
1328 <reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/>
1329 <reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/>
1330 <reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/>
1331 <reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/>
1332 <reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/>
1333 <reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/>
1334 <reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/>
1335 <reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/>
1336 <reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/>
1337 <reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/>
1338 <reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/>
1339 <reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/>
1340 <reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/>
1341 <reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/>
1342 <reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/>
1343 <reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/>
1344 <reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/>
1345 <reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/>
1346 <reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/>
1347 <reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/>
1348 <reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/>
1349 <reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/>
1350 <reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/>
1351 <reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/>
1352 <reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/>
1353 <reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/>
1354 <reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/>
1355 <reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/>
1356 <reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/>
1357 <reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/>
1358 <reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/>
1359 <reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/>
1360 <reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/>
1361 <reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/>
1362 <reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/>
1363 <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
1364 <reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/>
1365 <reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/>
1366 <reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/>
1367 <array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4">
1368 <reg32 offset="0x0" name="REG"/>
1370 <array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4">
1371 <reg32 offset="0x0" name="REG"/>
1373 <array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4">
1374 <reg32 offset="0x0" name="REG"/>
1376 <array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4">
1377 <reg32 offset="0x0" name="REG"/>
1379 <array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4">
1380 <reg32 offset="0x0" name="REG"/>
1382 <array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4">
1383 <reg32 offset="0x0" name="REG"/>
1385 <array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4">
1386 <reg32 offset="0x0" name="REG"/>
1388 <array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4">
1389 <reg32 offset="0x0" name="REG"/>
1391 <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/>
1392 <reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/>
1393 <reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/>
1394 <reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/>
1395 <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1399 <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/>
1400 <array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4">
1401 <reg32 offset="0x0" name="REG"/>
1404 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
1430 <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
1431 <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
1432 <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
1433 <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
1434 <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
1435 <reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/>
1436 <reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1437 <reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1438 <reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/>
1439 <reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/>
1440 <reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/>
1441 <reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/>
1442 <reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/>
1443 <reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/>
1444 <reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/>
1445 <reg32 offset="0x0189" name="RBBM_AHB_STATUS"/>
1446 <reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1447 <reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1448 <reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/>
1449 <reg32 offset="0x0191" name="RBBM_STATUS">
1450 <bitfield name="HI_BUSY" pos="0" type="boolean"/>
1472 <reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/>
1473 <reg32 offset="0x01b0" name="RBBM_POWER_STATUS">
1476 <reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/>
1479 <reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/>
1480 <reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/>
1481 <reg32 offset="0x0200" name="CP_RB_BASE"/>
1482 <reg32 offset="0x0201" name="CP_RB_CNTL"/>
1483 <reg32 offset="0x0205" name="CP_RB_WPTR"/>
1484 <reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/>
1485 <reg32 offset="0x0204" name="CP_RB_RPTR"/>
1486 <reg32 offset="0x0206" name="CP_IB1_BASE"/>
1487 <reg32 offset="0x0207" name="CP_IB1_BUFSZ"/>
1488 <reg32 offset="0x0208" name="CP_IB2_BASE"/>
1489 <reg32 offset="0x0209" name="CP_IB2_BUFSZ"/>
1490 <reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/>
1491 <reg32 offset="0x020d" name="CP_ME_NRT_DATA"/>
1492 <reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/>
1493 <reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/>
1494 <reg32 offset="0x021b" name="CP_MERCIU_SIZE"/>
1495 <reg32 offset="0x021c" name="CP_ROQ_ADDR"/>
1496 <reg32 offset="0x021d" name="CP_ROQ_DATA"/>
1497 <reg32 offset="0x021e" name="CP_MEQ_ADDR"/>
1498 <reg32 offset="0x021f" name="CP_MEQ_DATA"/>
1499 <reg32 offset="0x0220" name="CP_MERCIU_ADDR"/>
1500 <reg32 offset="0x0221" name="CP_MERCIU_DATA"/>
1501 <reg32 offset="0x0222" name="CP_MERCIU_DATA2"/>
1502 <reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/>
1503 <reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/>
1504 <reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/>
1505 <reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/>
1506 <reg32 offset="0x0227" name="CP_ME_RAM_DATA"/>
1507 <reg32 offset="0x022a" name="CP_PREEMPT"/>
1508 <reg32 offset="0x022c" name="CP_CNTL"/>
1509 <reg32 offset="0x022d" name="CP_ME_CNTL"/>
1510 <reg32 offset="0x022e" name="CP_DEBUG"/>
1511 <reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/>
1512 <reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/>
1513 <array offset="0x0240" name="CP_PROTECT" stride="1" length="16">
1514 <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
1516 <reg32 offset="0x0250" name="CP_PROTECT_CTRL"/>
1517 <reg32 offset="0x04c0" name="CP_ST_BASE"/>
1518 <reg32 offset="0x04ce" name="CP_STQ_AVAIL"/>
1519 <reg32 offset="0x04d0" name="CP_MERCIU_STAT"/>
1520 <reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/>
1521 <reg32 offset="0x04d8" name="CP_HW_FAULT"/>
1522 <reg32 offset="0x04da" name="CP_PROTECT_STATUS"/>
1523 <reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/>
1524 <reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/>
1525 <reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/>
1526 <reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/>
1527 <reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/>
1528 <reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/>
1529 <reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/>
1530 <reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/>
1531 <reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/>
1532 <reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/>
1533 <array offset="0x0578" name="CP_SCRATCH" stride="1" length="23">
1534 <reg32 offset="0x0" name="REG"/>
1539 <reg32 offset="0x0ec0" name="SP_VS_STATUS"/>
1540 <reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/>
1542 <reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/>
1543 <reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/>
1544 <reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/>
1545 <reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/>
1546 <reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/>
1547 <reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/>
1548 <reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/>
1549 <reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/>
1550 <reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/>
1551 <reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/>
1552 <reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/>
1553 <reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/>
1555 <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
1558 <reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL">
1573 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1596 <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1597 <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
1598 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1601 <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
1602 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1606 <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16">
1607 <reg32 offset="0x0" name="REG">
1608 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1614 <array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8">
1615 <reg32 offset="0x0" name="REG">
1618 Always seems to start from 8, possibly loc 0 and 4
1621 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1628 <reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG">
1639 <reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
1640 <reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>
1641 <reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
1642 <reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
1643 <reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1644 <reg32 offset="0x22e9" name="SP_FS_CTRL_REG1">
1645 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1650 <reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG">
1654 <reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
1655 <reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>
1656 <reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
1657 <reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
1658 <reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
1659 <bitfield name="MRT" low="0" high="3" type="uint"/>
1665 <array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8">
1666 <reg32 offset="0x0" name="REG">
1667 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1675 <reg32 offset="0x2300" name="SP_CS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1676 <reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
1677 <reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
1678 <reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
1679 <reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/>
1680 <reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/>
1681 <reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/>
1682 <reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG">
1686 <reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
1687 <reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>
1688 <reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
1689 <reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
1691 <reg32 offset="0x231a" name="SP_DS_PARAM_REG">
1692 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1695 <array offset="0x231b" name="SP_DS_OUT" stride="1" length="16">
1696 <reg32 offset="0x0" name="REG">
1697 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1703 <array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8">
1704 <reg32 offset="0x0" name="REG">
1707 Always seems to start from 8, possibly loc 0 and 4
1710 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1716 <reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG">
1720 <reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
1721 <reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>
1722 <reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
1723 <reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
1725 <reg32 offset="0x2341" name="SP_GS_PARAM_REG">
1726 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1730 <array offset="0x2342" name="SP_GS_OUT" stride="1" length="16">
1731 <reg32 offset="0x0" name="REG">
1732 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1738 <array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8">
1739 <reg32 offset="0x0" name="REG">
1742 Always seems to start from 8, possibly loc 0 and 4
1745 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1751 <reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG">
1755 <reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
1756 <reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>
1757 <reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
1758 <reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>
1761 <reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/>
1762 <reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/>
1763 <reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/>
1764 <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/>
1765 <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/>
1766 <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/>
1767 <reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/>
1768 <reg32 offset="0x2140" name="VPC_ATTR">
1769 <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
1775 <reg32 offset="0x2141" name="VPC_PACK">
1776 <bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/>
1780 <array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8">
1781 <reg32 offset="0x0" name="MODE"/>
1783 <array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
1784 <reg32 offset="0x0" name="MODE"/>
1787 <reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/>
1790 <reg32 offset="0x0c00" name="VSC_BIN_SIZE">
1791 <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1794 <reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/>
1795 <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/>
1796 <reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/>
1797 <array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8">
1798 <reg32 offset="0x0" name="REG">
1802 direction (0,0 is upper left, 0,1 is leftmost bin
1807 <bitfield name="X" low="0" high="9" type="uint"/>
1813 <array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8">
1814 <reg32 offset="0x0" name="REG"/>
1816 <array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8">
1817 <reg32 offset="0x0" name="REG"/>
1819 <reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/>
1820 <reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/>
1821 <reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/>
1824 <reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/>
1825 <reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/>
1826 <reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/>
1827 <reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/>
1828 <reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/>
1829 <reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/>
1830 <reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/>
1831 <reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/>
1832 <reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/>
1833 <reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/>
1834 <reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/>
1835 <reg32 offset="0x2200" name="VFD_CONTROL_0">
1840 <bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/>
1851 <reg32 offset="0x2201" name="VFD_CONTROL_1">
1853 <bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/>
1857 <reg32 offset="0x2202" name="VFD_CONTROL_2"/>
1858 <reg32 offset="0x2203" name="VFD_CONTROL_3">
1863 <reg32 offset="0x2204" name="VFD_CONTROL_4"/>
1864 <reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/>
1865 <array offset="0x220a" name="VFD_FETCH" stride="4" length="32">
1866 <reg32 offset="0x0" name="INSTR_0">
1867 <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
1872 <reg32 offset="0x1" name="INSTR_1"/>
1873 <reg32 offset="0x2" name="INSTR_2">
1874 <bitfield name="SIZE" low="0" high="31"/>
1876 <reg32 offset="0x3" name="INSTR_3">
1878 <bitfield name="STEPRATE" low="0" high="8" type="uint"/>
1881 <array offset="0x228a" name="VFD_DECODE" stride="1" length="32">
1882 <reg32 offset="0x0" name="INSTR">
1883 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
1898 <reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/>
1900 <reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/>
1901 <reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/>
1902 <reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/>
1903 <reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/>
1904 <reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/>
1905 <reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/>
1906 <reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/>
1907 <reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/>
1908 <reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/>
1909 <reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/>
1910 <reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT">
1911 <bitfield name="VS" low="0" high="7" type="uint"/>
1916 <reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
1917 <reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/>
1918 <reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/>
1919 <reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/>
1920 <reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT">
1921 <bitfield name="FS" low="0" high="7" type="uint"/>
1924 <reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
1925 <reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/>
1926 <reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/>
1927 <reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/>
1930 <reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/>
1931 <reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/>
1932 <reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/>
1933 <reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/>
1934 <reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/>
1935 <reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/>
1936 <reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/>
1937 <reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/>
1938 <reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/>
1939 <reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/>
1940 <reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL">
1946 <reg32 offset="0x2003" name="GRAS_CNTL">
1947 <bitfield name="IJ_PERSP" pos="0" type="boolean"/>
1950 <reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ">
1951 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1954 <reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1955 <reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1956 <reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1957 <reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1958 <reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1959 <reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1960 <reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX">
1961 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1964 <reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1965 <reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL">
1969 <reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1970 <reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1971 <reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/>
1972 <reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL">
1974 <bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1976 <reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL">
1977 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1986 <reg32 offset="0x207b" name="GRAS_SC_CONTROL">
1993 <reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1994 <reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1995 <reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1996 <reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1997 <reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/>
1998 <reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/>
2001 <reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/>
2002 <reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/>
2003 <reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/>
2004 <reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/>
2005 <reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/>
2006 <reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/>
2007 <reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/>
2008 <reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/>
2009 <reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/>
2010 <reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/>
2011 <reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/>
2012 <reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/>
2013 <reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/>
2014 <reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/>
2015 <reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/>
2018 <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/>
2019 <reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/>
2021 <reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/>
2022 <reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/>
2023 <reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/>
2024 <reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/>
2025 <reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/>
2026 <reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/>
2027 <reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/>
2028 <reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/>
2029 <reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/>
2030 <reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/>
2031 <reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG">
2044 <reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG">
2052 <reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG">
2058 <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
2060 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
2065 <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
2066 <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG">
2067 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
2072 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
2079 <reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2080 <reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2081 <reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2082 <reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2083 <reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2084 <reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2085 <reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0">
2086 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2092 <reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1">
2093 <bitfield name="SIZE_X" low="0" high="31" type="uint"/>
2095 <reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/>
2096 <reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3">
2097 <bitfield name="SIZE_Y" low="0" high="31" type="uint"/>
2099 <reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/>
2100 <reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5">
2101 <bitfield name="SIZE_Z" low="0" high="31" type="uint"/>
2103 <reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
2104 <reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
2105 <bitfield name="WGIDCONSTID" low="0" high="11" type="a3xx_regid"/>
2109 <reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1">
2111 <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2114 <reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST">
2116 <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2119 <reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
2120 <reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
2121 <reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
2122 <reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET">
2124 <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2126 <reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
2129 <reg32 offset="0x0d00" name="PC_BINNING_COMMAND">
2130 <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
2132 <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/>
2133 <reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/>
2134 <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/>
2135 <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/>
2136 <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/>
2137 <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/>
2138 <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/>
2139 <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/>
2140 <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/>
2141 <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/>
2142 <reg32 offset="0x21c0" name="PC_BIN_BASE"/>
2143 <reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL">
2147 N is some sort of slot # between 0..(SIZE-1). In case
2152 <reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL">
2154 <bitfield name="VAROUT" low="0" high="3" type="uint">
2156 0, 1, 2, 4, 6, 8</doc>
2163 <reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2">
2164 <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2168 <reg32 offset="0x21c6" name="PC_RESTART_INDEX"/>
2169 <reg32 offset="0x21e5" name="PC_GS_PARAM">
2170 <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 -->
2175 <reg32 offset="0x21e7" name="PC_HS_PARAM">
2176 <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2183 <reg32 offset="0x3000" name="VBIF_VERSION"/>
2184 <reg32 offset="0x3001" name="VBIF_CLKON">
2185 <bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/>
2187 <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
2188 <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
2189 <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
2190 <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
2191 <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
2192 <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
2193 <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
2194 <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
2195 <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
2196 <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
2197 <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
2198 <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
2199 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/>
2200 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/>
2201 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/>
2202 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/>
2203 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
2204 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
2205 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
2206 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
2207 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
2208 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
2209 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
2210 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
2211 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
2212 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
2213 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
2221 <reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/>
2224 <reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/>
2227 <reg32 offset="0x0d01" name="UNKNOWN_0D01"/>
2230 <reg32 offset="0x0e42" name="UNKNOWN_0E42"/>
2233 <reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/>
2236 <reg32 offset="0x2001" name="UNKNOWN_2001"/>
2239 <reg32 offset="0x209b" name="UNKNOWN_209B"/>
2242 <reg32 offset="0x20ef" name="UNKNOWN_20EF"/>
2245 <reg32 offset="0x2152" name="UNKNOWN_2152"/>
2248 <reg32 offset="0x2153" name="UNKNOWN_2153"/>
2251 <reg32 offset="0x2154" name="UNKNOWN_2154"/>
2254 <reg32 offset="0x2155" name="UNKNOWN_2155"/>
2257 <reg32 offset="0x2156" name="UNKNOWN_2156"/>
2260 <reg32 offset="0x2157" name="UNKNOWN_2157"/>
2263 <reg32 offset="0x21c3" name="UNKNOWN_21C3"/>
2266 <reg32 offset="0x21e6" name="UNKNOWN_21E6"/>
2269 <reg32 offset="0x2209" name="UNKNOWN_2209"/>
2272 <reg32 offset="0x22d7" name="UNKNOWN_22D7"/>
2275 <reg32 offset="0x2352" name="UNKNOWN_2352"/>
2283 <value name="A4XX_TEX_NEAREST" value="0"/>
2288 <value name="A4XX_TEX_REPEAT" value="0"/>
2295 <value name="A4XX_TEX_ANISO_1" value="0"/>
2301 <reg32 offset="0" name="0">
2302 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2325 <value name="A4XX_TEX_X" value="0"/>
2333 <value name="A4XX_TEX_1D" value="0"/>
2339 <reg32 offset="0" name="0">
2340 <bitfield name="TILED" pos="0" type="boolean"/>
2351 <bitfield name="HEIGHT" low="0" high="14" type="uint"/>
2356 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
2363 <bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/>
2372 <bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/>
2381 <reg32 offset="0" name="0">
2386 <bitfield name="PITCH" low="0" high="21" type="uint"/>
2393 <bitfield name="CPP" low="0" high="5" type="uint"/>
2398 <reg32 offset="0" name="0">
2399 <bitfield name="CPP" low="0" high="4" type="uint"/>
2404 <bitfield name="HEIGHT" low="0" high="15" type="uint"/>