Lines Matching +full:pll +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
24 * HDMI PLL:
26 * To get the parent clock setup properly, we need to plug in hdmi pll
27 * configuration into common-clock-framework.
237 static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) in pll_write() argument
239 writel(data, pll->mmio + reg); in pll_write()
242 static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg) in pll_read() argument
244 return readl(pll->mmio + reg); in pll_read()
247 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll) in pll_get_phy() argument
249 return platform_get_drvdata(pll->pdev); in pll_get_phy()
254 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); in hdmi_pll_enable() local
255 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_pll_enable()
261 /* Assert PLL S/W reset */ in hdmi_pll_enable()
262 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); in hdmi_pll_enable()
263 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10); in hdmi_pll_enable()
264 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a); in hdmi_pll_enable()
266 /* Wait for a short time before de-asserting in hdmi_pll_enable()
269 * to assert and de-assert. in hdmi_pll_enable()
273 /* De-assert PLL S/W reset */ in hdmi_pll_enable()
274 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); in hdmi_pll_enable()
278 /* Assert PHY S/W reset */ in hdmi_pll_enable()
282 * Wait for a short time before de-asserting to allow the hardware to in hdmi_pll_enable()
284 * assert and de-assert. in hdmi_pll_enable()
287 /* De-assert PHY S/W reset */ in hdmi_pll_enable()
298 val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); in hdmi_pll_enable()
301 pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); in hdmi_pll_enable()
305 while (--pll_lock_retry > 0) { in hdmi_pll_enable()
307 val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0); in hdmi_pll_enable()
313 if (--timeout_count > 0) in hdmi_pll_enable()
317 * PLL has still not locked. in hdmi_pll_enable()
318 * Do a software reset and try again in hdmi_pll_enable()
319 * Assert PLL S/W reset first in hdmi_pll_enable()
321 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); in hdmi_pll_enable()
323 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); in hdmi_pll_enable()
326 * Wait for a short duration for the PLL calibration in hdmi_pll_enable()
327 * before checking if the PLL gets locked in hdmi_pll_enable()
339 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); in hdmi_pll_disable() local
340 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_pll_disable()
349 val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); in hdmi_pll_disable()
352 pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); in hdmi_pll_disable()
353 /* Make sure HDMI PHY/PLL are powered down */ in hdmi_pll_disable()
363 return &freqtbl[i - 1]; in find_rate()
365 return &freqtbl[i - 1]; in find_rate()
371 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); in hdmi_pll_recalc_rate() local
373 return pll->pixclk; in hdmi_pll_recalc_rate()
381 return pll_rate->rate; in hdmi_pll_round_rate()
387 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); in hdmi_pll_set_rate() local
393 for (i = 0; i < pll_rate->num_reg; i++) in hdmi_pll_set_rate()
394 pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); in hdmi_pll_set_rate()
396 pll->pixclk = rate; in hdmi_pll_set_rate()
423 struct device *dev = &pdev->dev; in msm_hdmi_pll_8960_init()
424 struct hdmi_pll_8960 *pll; in msm_hdmi_pll_8960_init() local
428 for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++) in msm_hdmi_pll_8960_init()
430 return -EINVAL; in msm_hdmi_pll_8960_init()
432 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); in msm_hdmi_pll_8960_init()
433 if (!pll) in msm_hdmi_pll_8960_init()
434 return -ENOMEM; in msm_hdmi_pll_8960_init()
436 pll->mmio = msm_ioremap(pdev, "hdmi_pll"); in msm_hdmi_pll_8960_init()
437 if (IS_ERR(pll->mmio)) { in msm_hdmi_pll_8960_init()
438 DRM_DEV_ERROR(dev, "failed to map pll base\n"); in msm_hdmi_pll_8960_init()
439 return -ENOMEM; in msm_hdmi_pll_8960_init()
442 pll->pdev = pdev; in msm_hdmi_pll_8960_init()
443 pll->clk_hw.init = &pll_init; in msm_hdmi_pll_8960_init()
445 ret = devm_clk_hw_register(dev, &pll->clk_hw); in msm_hdmi_pll_8960_init()
447 DRM_DEV_ERROR(dev, "failed to register pll clock\n"); in msm_hdmi_pll_8960_init()
451 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw); in msm_hdmi_pll_8960_init()