Lines Matching +full:vco +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
98 int offset, int data) in hdmi_tx_chan_write() argument
100 writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
172 u64 vco, vco_optimal; in pll_get_post_div() local
179 vco_optimal_index = -1; in pll_get_post_div()
185 vco = bclk >> half_rate_mode; in pll_get_post_div()
186 vco *= ratio_mult; in pll_get_post_div()
187 vco_freq[vco_freq_index++] = vco; in pll_get_post_div()
201 if (vco_optimal_index == -1) { in pll_get_post_div()
207 pd->vco_freq = vco_optimal; in pll_get_post_div()
208 pd->tx_band_sel = tx_band_sel[vco_optimal_index % 4]; in pll_get_post_div()
209 pd->vco_ratio = ratio[vco_optimal_index / 4]; in pll_get_post_div()
210 pd->hsclk_divsel = hs_divsel[vco_optimal_index / 4]; in pll_get_post_div()
215 return -EINVAL; in pll_get_post_div()
255 frac_start -= dec_start * (1 << 20); in pll_calculate()
270 DBG("VCO freq: %llu", pd.vco_freq); in pll_calculate()
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
297 cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16); in pll_calculate()
298 cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff); in pll_calculate()
299 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()
300 cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff); in pll_calculate()
301 cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8); in pll_calculate()
302 cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); in pll_calculate()
303 cfg->com_lock_cmp_en = 0x0; in pll_calculate()
304 cfg->com_core_clk_en = 0x2c; in pll_calculate()
305 cfg->com_coreclk_div = HDMI_CORECLK_DIV; in pll_calculate()
306 cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; in pll_calculate()
307 cfg->com_vco_tune_ctrl = 0x0; in pll_calculate()
309 cfg->tx_lx_lane_mode[0] = in pll_calculate()
310 cfg->tx_lx_lane_mode[2] = 0x43; in pll_calculate()
312 cfg->tx_lx_hp_pd_enables[0] = in pll_calculate()
313 cfg->tx_lx_hp_pd_enables[1] = in pll_calculate()
314 cfg->tx_lx_hp_pd_enables[2] = 0x0c; in pll_calculate()
315 cfg->tx_lx_hp_pd_enables[3] = 0x3; in pll_calculate()
318 cfg->tx_lx_tx_band[i] = pd.tx_band_sel + 4; in pll_calculate()
321 cfg->tx_lx_tx_drv_lvl[0] = in pll_calculate()
322 cfg->tx_lx_tx_drv_lvl[1] = in pll_calculate()
323 cfg->tx_lx_tx_drv_lvl[2] = 0x25; in pll_calculate()
324 cfg->tx_lx_tx_drv_lvl[3] = 0x22; in pll_calculate()
326 cfg->tx_lx_tx_emp_post1_lvl[0] = in pll_calculate()
327 cfg->tx_lx_tx_emp_post1_lvl[1] = in pll_calculate()
328 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x23; in pll_calculate()
329 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x27; in pll_calculate()
331 cfg->tx_lx_vmode_ctrl1[0] = in pll_calculate()
332 cfg->tx_lx_vmode_ctrl1[1] = in pll_calculate()
333 cfg->tx_lx_vmode_ctrl1[2] = in pll_calculate()
334 cfg->tx_lx_vmode_ctrl1[3] = 0x00; in pll_calculate()
336 cfg->tx_lx_vmode_ctrl2[0] = in pll_calculate()
337 cfg->tx_lx_vmode_ctrl2[1] = in pll_calculate()
338 cfg->tx_lx_vmode_ctrl2[2] = 0x0D; in pll_calculate()
340 cfg->tx_lx_vmode_ctrl2[3] = 0x00; in pll_calculate()
343 cfg->tx_lx_tx_drv_lvl[i] = 0x25; in pll_calculate()
344 cfg->tx_lx_tx_emp_post1_lvl[i] = 0x23; in pll_calculate()
345 cfg->tx_lx_vmode_ctrl1[i] = 0x00; in pll_calculate()
348 cfg->tx_lx_vmode_ctrl2[0] = in pll_calculate()
349 cfg->tx_lx_vmode_ctrl2[1] = in pll_calculate()
350 cfg->tx_lx_vmode_ctrl2[2] = 0x0D; in pll_calculate()
351 cfg->tx_lx_vmode_ctrl2[3] = 0x00; in pll_calculate()
354 cfg->tx_lx_tx_drv_lvl[i] = 0x20; in pll_calculate()
355 cfg->tx_lx_tx_emp_post1_lvl[i] = 0x20; in pll_calculate()
356 cfg->tx_lx_vmode_ctrl1[i] = 0x00; in pll_calculate()
357 cfg->tx_lx_vmode_ctrl2[i] = 0x0E; in pll_calculate()
361 DBG("com_svs_mode_clk_sel = 0x%x", cfg->com_svs_mode_clk_sel); in pll_calculate()
362 DBG("com_hsclk_sel = 0x%x", cfg->com_hsclk_sel); in pll_calculate()
363 DBG("com_lock_cmp_en = 0x%x", cfg->com_lock_cmp_en); in pll_calculate()
364 DBG("com_pll_cctrl_mode0 = 0x%x", cfg->com_pll_cctrl_mode0); in pll_calculate()
365 DBG("com_pll_rctrl_mode0 = 0x%x", cfg->com_pll_rctrl_mode0); in pll_calculate()
366 DBG("com_cp_ctrl_mode0 = 0x%x", cfg->com_cp_ctrl_mode0); in pll_calculate()
367 DBG("com_dec_start_mode0 = 0x%x", cfg->com_dec_start_mode0); in pll_calculate()
368 DBG("com_div_frac_start1_mode0 = 0x%x", cfg->com_div_frac_start1_mode0); in pll_calculate()
369 DBG("com_div_frac_start2_mode0 = 0x%x", cfg->com_div_frac_start2_mode0); in pll_calculate()
370 DBG("com_div_frac_start3_mode0 = 0x%x", cfg->com_div_frac_start3_mode0); in pll_calculate()
371 DBG("com_integloop_gain0_mode0 = 0x%x", cfg->com_integloop_gain0_mode0); in pll_calculate()
372 DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0); in pll_calculate()
373 DBG("com_lock_cmp1_mode0 = 0x%x", cfg->com_lock_cmp1_mode0); in pll_calculate()
374 DBG("com_lock_cmp2_mode0 = 0x%x", cfg->com_lock_cmp2_mode0); in pll_calculate()
375 DBG("com_lock_cmp3_mode0 = 0x%x", cfg->com_lock_cmp3_mode0); in pll_calculate()
376 DBG("com_core_clk_en = 0x%x", cfg->com_core_clk_en); in pll_calculate()
377 DBG("com_coreclk_div = 0x%x", cfg->com_coreclk_div); in pll_calculate()
378 DBG("phy_mode = 0x%x", cfg->phy_mode); in pll_calculate()
380 DBG("tx_l0_lane_mode = 0x%x", cfg->tx_lx_lane_mode[0]); in pll_calculate()
381 DBG("tx_l2_lane_mode = 0x%x", cfg->tx_lx_lane_mode[2]); in pll_calculate()
384 DBG("tx_l%d_tx_band = 0x%x", i, cfg->tx_lx_tx_band[i]); in pll_calculate()
385 DBG("tx_l%d_tx_drv_lvl = 0x%x", i, cfg->tx_lx_tx_drv_lvl[i]); in pll_calculate()
387 cfg->tx_lx_tx_emp_post1_lvl[i]); in pll_calculate()
388 DBG("tx_l%d_vmode_ctrl1 = 0x%x", i, cfg->tx_lx_vmode_ctrl1[i]); in pll_calculate()
389 DBG("tx_l%d_vmode_ctrl2 = 0x%x", i, cfg->tx_lx_vmode_ctrl2[i]); in pll_calculate()
447 /* Bypass VCO calibration */ in hdmi_8996_pll_set_clk_rate()
535 * Ensure that vco configuration gets flushed to hardware before in hdmi_8996_pll_set_clk_rate()
552 while (nb_tries--) { in hdmi_8996_phy_ready_status()
576 while (nb_tries--) { in hdmi_8996_pll_lock_status()
706 struct device *dev = &pdev->dev; in msm_hdmi_pll_8996_init()
712 return -ENOMEM; in msm_hdmi_pll_8996_init()
714 pll->pdev = pdev; in msm_hdmi_pll_8996_init()
716 pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll"); in msm_hdmi_pll_8996_init()
717 if (IS_ERR(pll->mmio_qserdes_com)) { in msm_hdmi_pll_8996_init()
719 return -ENOMEM; in msm_hdmi_pll_8996_init()
727 pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name); in msm_hdmi_pll_8996_init()
728 if (IS_ERR(pll->mmio_qserdes_tx[i])) { in msm_hdmi_pll_8996_init()
730 return -ENOMEM; in msm_hdmi_pll_8996_init()
733 pll->clk_hw.init = &pll_init; in msm_hdmi_pll_8996_init()
735 ret = devm_clk_hw_register(dev, &pll->clk_hw); in msm_hdmi_pll_8996_init()
741 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw); in msm_hdmi_pll_8996_init()