13 	void __iomem *base = phy->base;  in dsi_20nm_dphy_set_timing()  local
16 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_0);  in dsi_20nm_dphy_set_timing()
18 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_1);  in dsi_20nm_dphy_set_timing()
20 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_2);  in dsi_20nm_dphy_set_timing()
23 		       base + REG_DSI_20nm_PHY_TIMING_CTRL_3);  in dsi_20nm_dphy_set_timing()
25 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_4);  in dsi_20nm_dphy_set_timing()
27 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_5);  in dsi_20nm_dphy_set_timing()
29 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_6);  in dsi_20nm_dphy_set_timing()
31 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_7);  in dsi_20nm_dphy_set_timing()
33 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_8);  in dsi_20nm_dphy_set_timing()
36 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_9);  in dsi_20nm_dphy_set_timing()
38 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_10);  in dsi_20nm_dphy_set_timing()
40 	       base + REG_DSI_20nm_PHY_TIMING_CTRL_11);  in dsi_20nm_dphy_set_timing()
45 	void __iomem *base = phy->reg_base;  in dsi_20nm_phy_regulator_ctrl()  local
48 		writel(0, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);  in dsi_20nm_phy_regulator_ctrl()
53 		writel(0x1d, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);  in dsi_20nm_phy_regulator_ctrl()
58 	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1);  in dsi_20nm_phy_regulator_ctrl()
59 	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2);  in dsi_20nm_phy_regulator_ctrl()
60 	writel(0x00, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3);  in dsi_20nm_phy_regulator_ctrl()
61 	writel(0x20, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4);  in dsi_20nm_phy_regulator_ctrl()
62 	writel(0x01, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);  in dsi_20nm_phy_regulator_ctrl()
63 	writel(0x00, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);  in dsi_20nm_phy_regulator_ctrl()
64 	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0);  in dsi_20nm_phy_regulator_ctrl()
72 	void __iomem *base = phy->base;  in dsi_20nm_phy_enable()  local
86 	writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0);  in dsi_20nm_phy_enable()
88 	val = readl(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);  in dsi_20nm_phy_enable()
93 	writel(val, base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);  in dsi_20nm_phy_enable()
96 		writel((i >> 1) * 0x40, base + REG_DSI_20nm_PHY_LN_CFG_3(i));  in dsi_20nm_phy_enable()
97 		writel(0x01, base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i));  in dsi_20nm_phy_enable()
98 		writel(0x46, base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i));  in dsi_20nm_phy_enable()
99 		writel(0x02, base + REG_DSI_20nm_PHY_LN_CFG_0(i));  in dsi_20nm_phy_enable()
100 		writel(0xa0, base + REG_DSI_20nm_PHY_LN_CFG_1(i));  in dsi_20nm_phy_enable()
101 		writel(cfg_4[i], base + REG_DSI_20nm_PHY_LN_CFG_4(i));  in dsi_20nm_phy_enable()
104 	writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3);  in dsi_20nm_phy_enable()
105 	writel(0x01, base + REG_DSI_20nm_PHY_LNCK_TEST_STR0);  in dsi_20nm_phy_enable()
106 	writel(0x46, base + REG_DSI_20nm_PHY_LNCK_TEST_STR1);  in dsi_20nm_phy_enable()
107 	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0);  in dsi_20nm_phy_enable()
108 	writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1);  in dsi_20nm_phy_enable()
109 	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2);  in dsi_20nm_phy_enable()
110 	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4);  in dsi_20nm_phy_enable()
114 	writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1);  in dsi_20nm_phy_enable()
116 	writel(0x06, base + REG_DSI_20nm_PHY_STRENGTH_1);  in dsi_20nm_phy_enable()
120 	writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0);  in dsi_20nm_phy_enable()
127 	writel(0, phy->base + REG_DSI_20nm_PHY_CTRL_0);  in dsi_20nm_phy_disable()