Lines Matching +full:dsi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
53 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc()
54 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc()
65 return -EINVAL; in msm_dsi_dphy_timing_calc()
70 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
71 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
72 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
78 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
83 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc()
84 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
85 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
86 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
89 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
91 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
92 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true); in msm_dsi_dphy_timing_calc()
95 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui; in msm_dsi_dphy_timing_calc()
96 temp = 145 * coeff + 10 * ui - temp; in msm_dsi_dphy_timing_calc()
97 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
98 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true); in msm_dsi_dphy_timing_calc()
100 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc()
101 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
103 tmin = DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
104 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
107 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
108 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true); in msm_dsi_dphy_timing_calc()
111 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
112 temp = 60 * coeff + 52 * ui - 24 * ui - temp; in msm_dsi_dphy_timing_calc()
113 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; in msm_dsi_dphy_timing_calc()
114 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, in msm_dsi_dphy_timing_calc()
117 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
118 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
120 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; in msm_dsi_dphy_timing_calc()
123 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc()
124 timing->shared_timings.clk_pre_inc_by_2 = true; in msm_dsi_dphy_timing_calc()
126 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc()
128 timing->shared_timings.clk_pre_inc_by_2 = false; in msm_dsi_dphy_timing_calc()
131 timing->ta_go = 3; in msm_dsi_dphy_timing_calc()
132 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc()
133 timing->ta_get = 4; in msm_dsi_dphy_timing_calc()
135 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", in msm_dsi_dphy_timing_calc()
136 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc()
137 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc()
138 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc()
139 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc()
140 timing->hs_rqst); in msm_dsi_dphy_timing_calc()
148 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v2()
149 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v2()
164 return -EINVAL; in msm_dsi_dphy_timing_calc_v2()
166 timing->hs_halfbyte_en = 0; in msm_dsi_dphy_timing_calc_v2()
168 timing->hs_halfbyte_en_ckln = 0; in msm_dsi_dphy_timing_calc_v2()
170 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3; in msm_dsi_dphy_timing_calc_v2()
171 pd_ckln = timing->hs_prep_dly_ckln; in msm_dsi_dphy_timing_calc_v2()
172 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1; in msm_dsi_dphy_timing_calc_v2()
173 pd = timing->hs_prep_dly; in msm_dsi_dphy_timing_calc_v2()
181 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8); in msm_dsi_dphy_timing_calc_v2()
183 temp = (95 * coeff - val_ckln * ui) / ui_x8; in msm_dsi_dphy_timing_calc_v2()
185 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); in msm_dsi_dphy_timing_calc_v2()
187 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui; in msm_dsi_dphy_timing_calc_v2()
188 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; in msm_dsi_dphy_timing_calc_v2()
190 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v2()
193 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v2()
195 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v2()
197 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8); in msm_dsi_dphy_timing_calc_v2()
199 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8; in msm_dsi_dphy_timing_calc_v2()
201 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); in msm_dsi_dphy_timing_calc_v2()
203 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui; in msm_dsi_dphy_timing_calc_v2()
204 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; in msm_dsi_dphy_timing_calc_v2()
206 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); in msm_dsi_dphy_timing_calc_v2()
209 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v2()
211 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v2()
213 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v2()
214 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v2()
216 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
218 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); in msm_dsi_dphy_timing_calc_v2()
220 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v2()
221 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v2()
223 temp = 60 * coeff + 52 * ui - 43 * ui; in msm_dsi_dphy_timing_calc_v2()
224 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
226 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v2()
229 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui; in msm_dsi_dphy_timing_calc_v2()
230 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; in msm_dsi_dphy_timing_calc_v2()
231 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : in msm_dsi_dphy_timing_calc_v2()
232 (((timing->hs_rqst_ckln << 3) + 8) * ui); in msm_dsi_dphy_timing_calc_v2()
233 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
237 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v2()
238 timing->shared_timings.clk_pre_inc_by_2 = 1; in msm_dsi_dphy_timing_calc_v2()
240 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v2()
242 timing->shared_timings.clk_pre_inc_by_2 = 0; in msm_dsi_dphy_timing_calc_v2()
245 timing->ta_go = 3; in msm_dsi_dphy_timing_calc_v2()
246 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc_v2()
247 timing->ta_get = 4; in msm_dsi_dphy_timing_calc_v2()
250 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v2()
251 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v2()
252 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v2()
253 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v2()
254 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v2()
255 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, in msm_dsi_dphy_timing_calc_v2()
256 timing->hs_prep_dly_ckln); in msm_dsi_dphy_timing_calc_v2()
264 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v3()
265 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v3()
279 return -EINVAL; in msm_dsi_dphy_timing_calc_v3()
281 timing->hs_halfbyte_en = 0; in msm_dsi_dphy_timing_calc_v3()
283 timing->hs_halfbyte_en_ckln = 0; in msm_dsi_dphy_timing_calc_v3()
293 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); in msm_dsi_dphy_timing_calc_v3()
295 temp = 300 * coeff - (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
296 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
298 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v3()
301 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v3()
303 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v3()
309 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); in msm_dsi_dphy_timing_calc_v3()
311 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
312 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
314 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); in msm_dsi_dphy_timing_calc_v3()
316 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
317 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v3()
318 tmax = (temp / ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
319 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v3()
321 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v3()
322 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v3()
324 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
326 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); in msm_dsi_dphy_timing_calc_v3()
328 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v3()
329 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v3()
331 temp = 60 * coeff + 52 * ui - 43 * ui; in msm_dsi_dphy_timing_calc_v3()
332 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
334 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v3()
337 temp = 8 * ui + (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
338 temp += (((timing->clk_zero + 3) << 3) + 11) * ui; in msm_dsi_dphy_timing_calc_v3()
339 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : in msm_dsi_dphy_timing_calc_v3()
340 (((timing->hs_rqst_ckln << 3) + 8) * ui); in msm_dsi_dphy_timing_calc_v3()
341 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
345 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v3()
346 timing->shared_timings.clk_pre_inc_by_2 = 1; in msm_dsi_dphy_timing_calc_v3()
348 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v3()
350 timing->shared_timings.clk_pre_inc_by_2 = 0; in msm_dsi_dphy_timing_calc_v3()
353 timing->shared_timings.byte_intf_clk_div_2 = true; in msm_dsi_dphy_timing_calc_v3()
355 timing->ta_go = 3; in msm_dsi_dphy_timing_calc_v3()
356 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc_v3()
357 timing->ta_get = 4; in msm_dsi_dphy_timing_calc_v3()
360 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v3()
361 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v3()
362 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v3()
363 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v3()
364 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v3()
365 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, in msm_dsi_dphy_timing_calc_v3()
366 timing->hs_prep_dly_ckln); in msm_dsi_dphy_timing_calc_v3()
374 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v4()
375 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v4()
390 return -EINVAL; in msm_dsi_dphy_timing_calc_v4()
406 timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false); in msm_dsi_dphy_timing_calc_v4()
408 temp = 300 * coeff - (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v4()
409 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
411 timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false); in msm_dsi_dphy_timing_calc_v4()
414 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v4()
416 timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false); in msm_dsi_dphy_timing_calc_v4()
422 timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false); in msm_dsi_dphy_timing_calc_v4()
424 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v4()
425 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
427 timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false); in msm_dsi_dphy_timing_calc_v4()
429 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
430 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v4()
431 tmax = (temp / ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
432 timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false); in msm_dsi_dphy_timing_calc_v4()
434 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v4()
435 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v4()
437 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
439 timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false); in msm_dsi_dphy_timing_calc_v4()
442 * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1 in msm_dsi_dphy_timing_calc_v4()
444 temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8; in msm_dsi_dphy_timing_calc_v4()
445 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1; in msm_dsi_dphy_timing_calc_v4()
447 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false); in msm_dsi_dphy_timing_calc_v4()
452 * final = roundup(val1/val2, 0) - 1 in msm_dsi_dphy_timing_calc_v4()
454 temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff; in msm_dsi_dphy_timing_calc_v4()
455 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1; in msm_dsi_dphy_timing_calc_v4()
457 timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin; in msm_dsi_dphy_timing_calc_v4()
459 timing->shared_timings.byte_intf_clk_div_2 = true; in msm_dsi_dphy_timing_calc_v4()
462 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v4()
463 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v4()
464 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst); in msm_dsi_dphy_timing_calc_v4()
472 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_cphy_timing_calc_v4()
473 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_cphy_timing_calc_v4()
480 return -EINVAL; in msm_dsi_cphy_timing_calc_v4()
489 timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false); in msm_dsi_cphy_timing_calc_v4()
493 timing->hs_rqst = linear_inter(tmax, tmin, 1, 0, false); in msm_dsi_cphy_timing_calc_v4()
495 tmin = DIV_ROUND_UP(100 * coeff, ui_x7) - 1; in msm_dsi_cphy_timing_calc_v4()
497 timing->hs_exit = linear_inter(tmax, tmin, 10, 0, false); in msm_dsi_cphy_timing_calc_v4()
501 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false); in msm_dsi_cphy_timing_calc_v4()
503 tmin = min_t(s32, 64, S_DIV_ROUND_UP(262 * coeff, ui_x7) - 1); in msm_dsi_cphy_timing_calc_v4()
505 timing->shared_timings.clk_pre = linear_inter(tmax, tmin, 20, 0, false); in msm_dsi_cphy_timing_calc_v4()
508 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_cphy_timing_calc_v4()
509 timing->clk_prepare, timing->hs_exit, timing->hs_rqst); in msm_dsi_cphy_timing_calc_v4()
514 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) in dsi_phy_enable_resource() argument
516 struct device *dev = &phy->pdev->dev; in dsi_phy_enable_resource()
523 ret = clk_prepare_enable(phy->ahb_clk); in dsi_phy_enable_resource()
532 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) in dsi_phy_disable_resource() argument
534 clk_disable_unprepare(phy->ahb_clk); in dsi_phy_disable_resource()
535 pm_runtime_put(&phy->pdev->dev); in dsi_phy_disable_resource()
540 { .compatible = "qcom,dsi-phy-28nm-hpm",
542 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
544 { .compatible = "qcom,dsi-phy-28nm-lp",
546 { .compatible = "qcom,dsi-phy-28nm-8226",
548 { .compatible = "qcom,dsi-phy-28nm-8937",
552 { .compatible = "qcom,dsi-phy-20nm",
556 { .compatible = "qcom,dsi-phy-28nm-8960",
560 { .compatible = "qcom,dsi-phy-14nm",
562 { .compatible = "qcom,dsi-phy-14nm-2290",
564 { .compatible = "qcom,dsi-phy-14nm-660",
566 { .compatible = "qcom,dsi-phy-14nm-8953",
568 { .compatible = "qcom,sm6125-dsi-phy-14nm",
572 { .compatible = "qcom,dsi-phy-10nm",
574 { .compatible = "qcom,dsi-phy-10nm-8998",
578 { .compatible = "qcom,dsi-phy-7nm",
580 { .compatible = "qcom,dsi-phy-7nm-8150",
582 { .compatible = "qcom,sc7280-dsi-phy-7nm",
584 { .compatible = "qcom,sm6375-dsi-phy-7nm",
586 { .compatible = "qcom,sm8350-dsi-phy-5nm",
588 { .compatible = "qcom,sm8450-dsi-phy-5nm",
590 { .compatible = "qcom,sm8550-dsi-phy-4nm",
592 { .compatible = "qcom,sm8650-dsi-phy-4nm",
599 * Currently, we only support one SoC for each PHY type. When we have multiple
600 * SoCs for the same PHY, we can try to make the index searching a bit more
603 static int dsi_phy_get_id(struct msm_dsi_phy *phy) in dsi_phy_get_id() argument
605 struct platform_device *pdev = phy->pdev; in dsi_phy_get_id()
606 const struct msm_dsi_phy_cfg *cfg = phy->cfg; in dsi_phy_get_id()
612 return -EINVAL; in dsi_phy_get_id()
614 for (i = 0; i < cfg->num_dsi_phy; i++) { in dsi_phy_get_id()
615 if (cfg->io_start[i] == res->start) in dsi_phy_get_id()
619 return -EINVAL; in dsi_phy_get_id()
624 struct msm_dsi_phy *phy; in dsi_phy_driver_probe() local
625 struct device *dev = &pdev->dev; in dsi_phy_driver_probe()
629 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in dsi_phy_driver_probe()
630 if (!phy) in dsi_phy_driver_probe()
631 return -ENOMEM; in dsi_phy_driver_probe()
633 phy->provided_clocks = devm_kzalloc(dev, in dsi_phy_driver_probe()
634 struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS), in dsi_phy_driver_probe()
636 if (!phy->provided_clocks) in dsi_phy_driver_probe()
637 return -ENOMEM; in dsi_phy_driver_probe()
639 phy->provided_clocks->num = NUM_PROVIDED_CLKS; in dsi_phy_driver_probe()
641 phy->cfg = of_device_get_match_data(&pdev->dev); in dsi_phy_driver_probe()
642 if (!phy->cfg) in dsi_phy_driver_probe()
643 return -ENODEV; in dsi_phy_driver_probe()
645 phy->pdev = pdev; in dsi_phy_driver_probe()
647 phy->id = dsi_phy_get_id(phy); in dsi_phy_driver_probe()
648 if (phy->id < 0) in dsi_phy_driver_probe()
649 return dev_err_probe(dev, phy->id, in dsi_phy_driver_probe()
650 "Couldn't identify PHY index\n"); in dsi_phy_driver_probe()
652 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node, in dsi_phy_driver_probe()
653 "qcom,dsi-phy-regulator-ldo-mode"); in dsi_phy_driver_probe()
654 if (!of_property_read_u32(dev->of_node, "phy-type", &phy_type)) in dsi_phy_driver_probe()
655 phy->cphy_mode = (phy_type == PHY_TYPE_CPHY); in dsi_phy_driver_probe()
657 phy->base = msm_ioremap_size(pdev, "dsi_phy", &phy->base_size); in dsi_phy_driver_probe()
658 if (IS_ERR(phy->base)) in dsi_phy_driver_probe()
659 return dev_err_probe(dev, PTR_ERR(phy->base), in dsi_phy_driver_probe()
660 "Failed to map phy base\n"); in dsi_phy_driver_probe()
662 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size); in dsi_phy_driver_probe()
663 if (IS_ERR(phy->pll_base)) in dsi_phy_driver_probe()
664 return dev_err_probe(dev, PTR_ERR(phy->pll_base), in dsi_phy_driver_probe()
667 if (phy->cfg->has_phy_lane) { in dsi_phy_driver_probe()
668 phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", &phy->lane_size); in dsi_phy_driver_probe()
669 if (IS_ERR(phy->lane_base)) in dsi_phy_driver_probe()
670 return dev_err_probe(dev, PTR_ERR(phy->lane_base), in dsi_phy_driver_probe()
671 "Failed to map phy lane base\n"); in dsi_phy_driver_probe()
674 if (phy->cfg->has_phy_regulator) { in dsi_phy_driver_probe()
675 phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", &phy->reg_size); in dsi_phy_driver_probe()
676 if (IS_ERR(phy->reg_base)) in dsi_phy_driver_probe()
677 return dev_err_probe(dev, PTR_ERR(phy->reg_base), in dsi_phy_driver_probe()
678 "Failed to map phy regulator base\n"); in dsi_phy_driver_probe()
681 if (phy->cfg->ops.parse_dt_properties) { in dsi_phy_driver_probe()
682 ret = phy->cfg->ops.parse_dt_properties(phy); in dsi_phy_driver_probe()
687 ret = devm_regulator_bulk_get_const(dev, phy->cfg->num_regulators, in dsi_phy_driver_probe()
688 phy->cfg->regulator_data, in dsi_phy_driver_probe()
689 &phy->supplies); in dsi_phy_driver_probe()
693 phy->ahb_clk = msm_clk_get(pdev, "iface"); in dsi_phy_driver_probe()
694 if (IS_ERR(phy->ahb_clk)) in dsi_phy_driver_probe()
695 return dev_err_probe(dev, PTR_ERR(phy->ahb_clk), in dsi_phy_driver_probe()
698 ret = devm_pm_runtime_enable(&pdev->dev); in dsi_phy_driver_probe()
705 ret = dsi_phy_enable_resource(phy); in dsi_phy_driver_probe()
709 if (phy->cfg->ops.pll_init) { in dsi_phy_driver_probe()
710 ret = phy->cfg->ops.pll_init(phy); in dsi_phy_driver_probe()
717 phy->provided_clocks); in dsi_phy_driver_probe()
722 dsi_phy_disable_resource(phy); in dsi_phy_driver_probe()
724 platform_set_drvdata(pdev, phy); in dsi_phy_driver_probe()
747 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, in msm_dsi_phy_enable() argument
754 if (!phy || !phy->cfg->ops.enable) in msm_dsi_phy_enable()
755 return -EINVAL; in msm_dsi_phy_enable()
757 dev = &phy->pdev->dev; in msm_dsi_phy_enable()
759 ret = dsi_phy_enable_resource(phy); in msm_dsi_phy_enable()
766 ret = regulator_bulk_enable(phy->cfg->num_regulators, phy->supplies); in msm_dsi_phy_enable()
773 ret = phy->cfg->ops.enable(phy, clk_req); in msm_dsi_phy_enable()
775 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret); in msm_dsi_phy_enable()
779 memcpy(shared_timings, &phy->timing.shared_timings, in msm_dsi_phy_enable()
783 * Resetting DSI PHY silently changes its PLL registers to reset status, in msm_dsi_phy_enable()
788 if (phy->usecase != MSM_DSI_PHY_SLAVE) { in msm_dsi_phy_enable()
789 ret = msm_dsi_phy_pll_restore_state(phy); in msm_dsi_phy_enable()
791 DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n", in msm_dsi_phy_enable()
800 if (phy->cfg->ops.disable) in msm_dsi_phy_enable()
801 phy->cfg->ops.disable(phy); in msm_dsi_phy_enable()
803 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); in msm_dsi_phy_enable()
805 dsi_phy_disable_resource(phy); in msm_dsi_phy_enable()
810 void msm_dsi_phy_disable(struct msm_dsi_phy *phy) in msm_dsi_phy_disable() argument
812 if (!phy || !phy->cfg->ops.disable) in msm_dsi_phy_disable()
815 phy->cfg->ops.disable(phy); in msm_dsi_phy_disable()
817 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); in msm_dsi_phy_disable()
818 dsi_phy_disable_resource(phy); in msm_dsi_phy_disable()
821 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, in msm_dsi_phy_set_usecase() argument
824 if (phy) in msm_dsi_phy_set_usecase()
825 phy->usecase = uc; in msm_dsi_phy_set_usecase()
829 bool msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) in msm_dsi_phy_set_continuous_clock() argument
831 if (!phy || !phy->cfg->ops.set_continuous_clock) in msm_dsi_phy_set_continuous_clock()
834 return phy->cfg->ops.set_continuous_clock(phy, enable); in msm_dsi_phy_set_continuous_clock()
837 void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy) in msm_dsi_phy_pll_save_state() argument
839 if (phy->cfg->ops.save_pll_state) { in msm_dsi_phy_pll_save_state()
840 phy->cfg->ops.save_pll_state(phy); in msm_dsi_phy_pll_save_state()
841 phy->state_saved = true; in msm_dsi_phy_pll_save_state()
845 int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy) in msm_dsi_phy_pll_restore_state() argument
849 if (phy->cfg->ops.restore_pll_state && phy->state_saved) { in msm_dsi_phy_pll_restore_state()
850 ret = phy->cfg->ops.restore_pll_state(phy); in msm_dsi_phy_pll_restore_state()
854 phy->state_saved = false; in msm_dsi_phy_pll_restore_state()
860 void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy) in msm_dsi_phy_snapshot() argument
863 phy->base_size, phy->base, in msm_dsi_phy_snapshot()
864 "dsi%d_phy", phy->id); in msm_dsi_phy_snapshot()
867 if (phy->pll_on) in msm_dsi_phy_snapshot()
869 phy->pll_size, phy->pll_base, in msm_dsi_phy_snapshot()
870 "dsi%d_pll", phy->id); in msm_dsi_phy_snapshot()
872 if (phy->lane_base) in msm_dsi_phy_snapshot()
874 phy->lane_size, phy->lane_base, in msm_dsi_phy_snapshot()
875 "dsi%d_lane", phy->id); in msm_dsi_phy_snapshot()
877 if (phy->reg_base) in msm_dsi_phy_snapshot()
879 phy->reg_size, phy->reg_base, in msm_dsi_phy_snapshot()
880 "dsi%d_reg", phy->id); in msm_dsi_phy_snapshot()