Lines Matching +full:dsi +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
26 #include "dsi.h"
27 #include "dsi.xml.h"
44 return -EINVAL; in dsi_get_version()
48 * makes all other registers 4-byte shifted down. in dsi_get_version()
52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In in dsi_get_version()
59 /* older dsi host, there is no register shift */ in dsi_get_version()
67 return -EINVAL; in dsi_get_version()
83 return -EINVAL; in dsi_get_version()
127 /* DSI v2 specific clocks */
144 /* DSI 6G TX buffer*/
148 /* DSI v2 TX buffer */
185 return readl(msm_host->ctrl_base + reg); in dsi_read()
189 writel(data, msm_host->ctrl_base + reg); in dsi_write()
196 struct device *dev = &msm_host->pdev->dev; in dsi_get_config()
201 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); in dsi_get_config()
215 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); in dsi_get_config()
240 struct platform_device *pdev = msm_host->pdev; in dsi_clk_init_v2()
243 msm_host->src_clk = msm_clk_get(pdev, "src"); in dsi_clk_init_v2()
245 if (IS_ERR(msm_host->src_clk)) { in dsi_clk_init_v2()
246 ret = PTR_ERR(msm_host->src_clk); in dsi_clk_init_v2()
249 msm_host->src_clk = NULL; in dsi_clk_init_v2()
258 struct platform_device *pdev = msm_host->pdev; in dsi_clk_init_6g_v2()
261 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); in dsi_clk_init_6g_v2()
262 if (IS_ERR(msm_host->byte_intf_clk)) { in dsi_clk_init_6g_v2()
263 ret = PTR_ERR(msm_host->byte_intf_clk); in dsi_clk_init_6g_v2()
273 struct platform_device *pdev = msm_host->pdev; in dsi_clk_init()
274 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in dsi_clk_init()
275 const struct msm_dsi_config *cfg = cfg_hnd->cfg; in dsi_clk_init()
279 for (i = 0; i < cfg->num_bus_clks; i++) in dsi_clk_init()
280 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; in dsi_clk_init()
281 msm_host->num_bus_clks = cfg->num_bus_clks; in dsi_clk_init()
283 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); in dsi_clk_init()
285 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); in dsi_clk_init()
290 msm_host->byte_clk = msm_clk_get(pdev, "byte"); in dsi_clk_init()
291 if (IS_ERR(msm_host->byte_clk)) { in dsi_clk_init()
292 ret = PTR_ERR(msm_host->byte_clk); in dsi_clk_init()
295 msm_host->byte_clk = NULL; in dsi_clk_init()
299 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
300 if (IS_ERR(msm_host->pixel_clk)) { in dsi_clk_init()
301 ret = PTR_ERR(msm_host->pixel_clk); in dsi_clk_init()
304 msm_host->pixel_clk = NULL; in dsi_clk_init()
308 msm_host->esc_clk = msm_clk_get(pdev, "core"); in dsi_clk_init()
309 if (IS_ERR(msm_host->esc_clk)) { in dsi_clk_init()
310 ret = PTR_ERR(msm_host->esc_clk); in dsi_clk_init()
313 msm_host->esc_clk = NULL; in dsi_clk_init()
317 if (cfg_hnd->ops->clk_init_ver) in dsi_clk_init()
318 ret = cfg_hnd->ops->clk_init_ver(msm_host); in dsi_clk_init()
327 struct mipi_dsi_host *host = msm_dsi->host; in msm_dsi_runtime_suspend()
330 if (!msm_host->cfg_hnd) in msm_dsi_runtime_suspend()
333 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); in msm_dsi_runtime_suspend()
342 struct mipi_dsi_host *host = msm_dsi->host; in msm_dsi_runtime_resume()
345 if (!msm_host->cfg_hnd) in msm_dsi_runtime_resume()
348 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); in msm_dsi_runtime_resume()
356 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); in dsi_link_clk_set_rate_6g()
358 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, in dsi_link_clk_set_rate_6g()
359 msm_host->byte_clk_rate); in dsi_link_clk_set_rate_6g()
365 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
371 if (msm_host->byte_intf_clk) { in dsi_link_clk_set_rate_6g()
372 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); in dsi_link_clk_set_rate_6g()
388 ret = clk_prepare_enable(msm_host->esc_clk); in dsi_link_clk_enable_6g()
390 pr_err("%s: Failed to enable dsi esc clk\n", __func__); in dsi_link_clk_enable_6g()
394 ret = clk_prepare_enable(msm_host->byte_clk); in dsi_link_clk_enable_6g()
396 pr_err("%s: Failed to enable dsi byte clk\n", __func__); in dsi_link_clk_enable_6g()
400 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
402 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); in dsi_link_clk_enable_6g()
406 ret = clk_prepare_enable(msm_host->byte_intf_clk); in dsi_link_clk_enable_6g()
416 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
418 clk_disable_unprepare(msm_host->byte_clk); in dsi_link_clk_enable_6g()
420 clk_disable_unprepare(msm_host->esc_clk); in dsi_link_clk_enable_6g()
430 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, in dsi_link_clk_set_rate_v2()
431 msm_host->esc_clk_rate, msm_host->src_clk_rate); in dsi_link_clk_set_rate_v2()
433 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); in dsi_link_clk_set_rate_v2()
439 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); in dsi_link_clk_set_rate_v2()
445 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); in dsi_link_clk_set_rate_v2()
451 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
464 ret = clk_prepare_enable(msm_host->byte_clk); in dsi_link_clk_enable_v2()
466 pr_err("%s: Failed to enable dsi byte clk\n", __func__); in dsi_link_clk_enable_v2()
470 ret = clk_prepare_enable(msm_host->esc_clk); in dsi_link_clk_enable_v2()
472 pr_err("%s: Failed to enable dsi esc clk\n", __func__); in dsi_link_clk_enable_v2()
476 ret = clk_prepare_enable(msm_host->src_clk); in dsi_link_clk_enable_v2()
478 pr_err("%s: Failed to enable dsi src clk\n", __func__); in dsi_link_clk_enable_v2()
482 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_v2()
484 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); in dsi_link_clk_enable_v2()
491 clk_disable_unprepare(msm_host->src_clk); in dsi_link_clk_enable_v2()
493 clk_disable_unprepare(msm_host->esc_clk); in dsi_link_clk_enable_v2()
495 clk_disable_unprepare(msm_host->byte_clk); in dsi_link_clk_enable_v2()
503 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); in dsi_link_clk_disable_6g()
504 clk_disable_unprepare(msm_host->esc_clk); in dsi_link_clk_disable_6g()
505 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_disable_6g()
506 clk_disable_unprepare(msm_host->byte_intf_clk); in dsi_link_clk_disable_6g()
507 clk_disable_unprepare(msm_host->byte_clk); in dsi_link_clk_disable_6g()
512 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_disable_v2()
513 clk_disable_unprepare(msm_host->src_clk); in dsi_link_clk_disable_v2()
514 clk_disable_unprepare(msm_host->esc_clk); in dsi_link_clk_disable_v2()
515 clk_disable_unprepare(msm_host->byte_clk); in dsi_link_clk_disable_v2()
519 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case
520 * @mode: The selected mode for the DSI output
521 * @dsc: DRM DSC configuration for this DSI output
528 * - For VIDEO mode they are not compressed by DSC and are passed as is.
529 * - For CMD mode there are no actual porches. Instead these fields
540 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), in dsi_adjust_pclk_for_compression()
541 dsc->bits_per_component * 3); in dsi_adjust_pclk_for_compression()
543 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; in dsi_adjust_pclk_for_compression()
545 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); in dsi_adjust_pclk_for_compression()
553 pclk_rate = mode->clock * 1000u; in dsi_get_pclk_rate()
559 * For bonded DSI mode, the current DRM mode has the complete width of the in dsi_get_pclk_rate()
560 * panel. Since, the complete panel is driven by two DSI controllers, in dsi_get_pclk_rate()
561 * the clock rates have to be split between the two dsi controllers. in dsi_get_pclk_rate()
562 * Adjust the byte and pixel clock rates for each dsi host accordingly. in dsi_get_pclk_rate()
574 u8 lanes = msm_host->lanes; in dsi_byte_clk_get_rate()
575 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); in dsi_byte_clk_get_rate()
576 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); in dsi_byte_clk_get_rate()
585 if (msm_host->cphy_mode) in dsi_byte_clk_get_rate()
595 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); in dsi_calc_pclk()
596 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, in dsi_calc_pclk()
597 msm_host->mode); in dsi_calc_pclk()
599 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, in dsi_calc_pclk()
600 msm_host->byte_clk_rate); in dsi_calc_pclk()
606 if (!msm_host->mode) { in dsi_calc_clk_rate_6g()
608 return -EINVAL; in dsi_calc_clk_rate_6g()
612 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); in dsi_calc_clk_rate_6g()
618 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); in dsi_calc_clk_rate_v2()
624 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); in dsi_calc_clk_rate_v2()
629 * mipi DSI spec range within the maximum divider limit in dsi_calc_clk_rate_v2()
635 byte_mhz = msm_host->byte_clk_rate / 1000000; in dsi_calc_clk_rate_v2()
637 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { in dsi_calc_clk_rate_v2()
651 return -EINVAL; in dsi_calc_clk_rate_v2()
653 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; in dsi_calc_clk_rate_v2()
655 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, in dsi_calc_clk_rate_v2()
656 msm_host->src_clk_rate); in dsi_calc_clk_rate_v2()
666 spin_lock_irqsave(&msm_host->intr_lock, flags); in dsi_intr_ctrl()
677 spin_unlock_irqrestore(&msm_host->intr_lock, flags); in dsi_intr_ctrl()
723 return msm_host->dsc && in msm_dsi_host_is_wide_bus_enabled()
724 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && in msm_dsi_host_is_wide_bus_enabled()
725 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); in msm_dsi_host_is_wide_bus_enabled()
731 u32 flags = msm_host->mode_flags; in dsi_ctrl_enable()
732 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; in dsi_ctrl_enable()
733 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in dsi_ctrl_enable()
752 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); in dsi_ctrl_enable()
753 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) in dsi_ctrl_enable()
773 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { in dsi_ctrl_enable()
776 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) in dsi_ctrl_enable()
779 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) in dsi_ctrl_enable()
795 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); in dsi_ctrl_enable()
796 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && in dsi_ctrl_enable()
797 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) in dsi_ctrl_enable()
801 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | in dsi_ctrl_enable()
802 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); in dsi_ctrl_enable()
805 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && in dsi_ctrl_enable()
806 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && in dsi_ctrl_enable()
807 phy_shared_timings->clk_pre_inc_by_2) in dsi_ctrl_enable()
816 /* allow only ack-err-status to generate interrupt */ in dsi_ctrl_enable()
825 DBG("lane number=%d", msm_host->lanes); in dsi_ctrl_enable()
826 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); in dsi_ctrl_enable()
829 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); in dsi_ctrl_enable()
845 if (msm_host->cphy_mode) in dsi_ctrl_enable()
851 struct drm_dsc_config *dsc = msm_host->dsc; in dsi_update_dsc_timing()
863 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; in dsi_update_dsc_timing()
864 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ in dsi_update_dsc_timing()
888 drm_warn_once(msm_host->dev, "pkt_per_line too big"); in dsi_update_dsc_timing()
901 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()
913 struct drm_display_mode *mode = msm_host->mode; in dsi_timing_setup()
915 u32 h_total = mode->htotal; in dsi_timing_setup()
916 u32 v_total = mode->vtotal; in dsi_timing_setup()
917 u32 hs_end = mode->hsync_end - mode->hsync_start; in dsi_timing_setup()
918 u32 vs_end = mode->vsync_end - mode->vsync_start; in dsi_timing_setup()
919 u32 ha_start = h_total - mode->hsync_start; in dsi_timing_setup()
920 u32 ha_end = ha_start + mode->hdisplay; in dsi_timing_setup()
921 u32 va_start = v_total - mode->vsync_start; in dsi_timing_setup()
922 u32 va_end = va_start + mode->vdisplay; in dsi_timing_setup()
923 u32 hdisplay = mode->hdisplay; in dsi_timing_setup()
926 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); in dsi_timing_setup()
931 * For bonded DSI mode, the current DRM mode has in dsi_timing_setup()
933 * panel is driven by two DSI controllers, the horizontal in dsi_timing_setup()
934 * timings have to be split between the two dsi controllers. in dsi_timing_setup()
935 * Adjust the DSI host timing values accordingly. in dsi_timing_setup()
945 if (msm_host->dsc) { in dsi_timing_setup()
946 struct drm_dsc_config *dsc = msm_host->dsc; in dsi_timing_setup()
950 if (!dsc || !mode->hdisplay || !mode->vdisplay) { in dsi_timing_setup()
951 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", in dsi_timing_setup()
952 mode->hdisplay, mode->vdisplay); in dsi_timing_setup()
956 dsc->pic_width = mode->hdisplay; in dsi_timing_setup()
957 dsc->pic_height = mode->vdisplay; in dsi_timing_setup()
958 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); in dsi_timing_setup()
968 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is in dsi_timing_setup()
980 h_total -= hdisplay; in dsi_timing_setup()
981 if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) in dsi_timing_setup()
986 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); in dsi_timing_setup()
992 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { in dsi_timing_setup()
993 if (msm_host->dsc) in dsi_timing_setup()
994 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); in dsi_timing_setup()
1003 DSI_TOTAL_H_TOTAL(h_total - 1) | in dsi_timing_setup()
1004 DSI_TOTAL_V_TOTAL(v_total - 1)); in dsi_timing_setup()
1014 if (msm_host->dsc) in dsi_timing_setup()
1015 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); in dsi_timing_setup()
1018 if (!msm_host->dsc) in dsi_timing_setup()
1019 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; in dsi_timing_setup()
1028 wc = msm_host->dsc->slice_chunk_size + 1; in dsi_timing_setup()
1033 msm_host->channel) | in dsi_timing_setup()
1039 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); in dsi_timing_setup()
1052 * dsi controller need to be disabled before in dsi_sw_reset()
1061 /* dsi controller can only be reset while clocks are running */ in dsi_sw_reset()
1069 wmb(); /* make sure dsi controller enabled again */ in dsi_sw_reset()
1115 struct device *dev = &msm_host->pdev->dev; in dsi_wait4video_done()
1119 reinit_completion(&msm_host->video_comp); in dsi_wait4video_done()
1121 ret = wait_for_completion_timeout(&msm_host->video_comp, in dsi_wait4video_done()
1134 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) in dsi_wait4video_eng_busy()
1141 * DSI controller has finished transmitting the video in dsi_wait4video_eng_busy()
1147 if (msm_host->power_on && msm_host->enabled) { in dsi_wait4video_eng_busy()
1156 struct drm_device *dev = msm_host->dev; in dsi_tx_buf_alloc_6g()
1157 struct msm_drm_private *priv = dev->dev_private; in dsi_tx_buf_alloc_6g()
1161 msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace); in dsi_tx_buf_alloc_6g()
1164 msm_host->aspace, in dsi_tx_buf_alloc_6g()
1165 &msm_host->tx_gem_obj, &iova); in dsi_tx_buf_alloc_6g()
1168 msm_host->tx_gem_obj = NULL; in dsi_tx_buf_alloc_6g()
1172 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); in dsi_tx_buf_alloc_6g()
1174 msm_host->tx_size = msm_host->tx_gem_obj->size; in dsi_tx_buf_alloc_6g()
1181 struct drm_device *dev = msm_host->dev; in dsi_tx_buf_alloc_v2()
1183 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, in dsi_tx_buf_alloc_v2()
1184 &msm_host->tx_buf_paddr, GFP_KERNEL); in dsi_tx_buf_alloc_v2()
1185 if (!msm_host->tx_buf) in dsi_tx_buf_alloc_v2()
1186 return -ENOMEM; in dsi_tx_buf_alloc_v2()
1188 msm_host->tx_size = size; in dsi_tx_buf_alloc_v2()
1196 struct drm_device *dev = msm_host->dev; in msm_dsi_tx_buf_free()
1207 if (msm_host->tx_gem_obj) { in msm_dsi_tx_buf_free()
1208 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace); in msm_dsi_tx_buf_free()
1209 msm_gem_address_space_put(msm_host->aspace); in msm_dsi_tx_buf_free()
1210 msm_host->tx_gem_obj = NULL; in msm_dsi_tx_buf_free()
1211 msm_host->aspace = NULL; in msm_dsi_tx_buf_free()
1214 if (msm_host->tx_buf) in msm_dsi_tx_buf_free()
1215 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, in msm_dsi_tx_buf_free()
1216 msm_host->tx_buf_paddr); in msm_dsi_tx_buf_free()
1221 return msm_gem_get_vaddr(msm_host->tx_gem_obj); in dsi_tx_buf_get_6g()
1226 return msm_host->tx_buf; in dsi_tx_buf_get_v2()
1231 msm_gem_put_vaddr(msm_host->tx_gem_obj); in dsi_tx_buf_put_6g()
1240 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in dsi_cmd_dma_add()
1253 if (len > msm_host->tx_size) { in dsi_cmd_dma_add()
1255 return -EINVAL; in dsi_cmd_dma_add()
1258 data = cfg_hnd->ops->tx_buf_get(msm_host); in dsi_cmd_dma_add()
1270 if (mipi_dsi_packet_format_is_long(msg->type)) in dsi_cmd_dma_add()
1272 if (msg->rx_buf && msg->rx_len) in dsi_cmd_dma_add()
1281 memset(data + packet.size, 0xff, len - packet.size); in dsi_cmd_dma_add()
1283 if (cfg_hnd->ops->tx_buf_put) in dsi_cmd_dma_add()
1284 cfg_hnd->ops->tx_buf_put(msm_host); in dsi_cmd_dma_add()
1294 u8 *data = msg->rx_buf; in dsi_short_read1_resp()
1295 if (data && (msg->rx_len >= 1)) { in dsi_short_read1_resp()
1300 __func__, msg->rx_len); in dsi_short_read1_resp()
1301 return -EINVAL; in dsi_short_read1_resp()
1310 u8 *data = msg->rx_buf; in dsi_short_read2_resp()
1311 if (data && (msg->rx_len >= 2)) { in dsi_short_read2_resp()
1317 __func__, msg->rx_len); in dsi_short_read2_resp()
1318 return -EINVAL; in dsi_short_read2_resp()
1325 if (msg->rx_buf && msg->rx_len) in dsi_long_read_resp()
1326 memcpy(msg->rx_buf, buf + 4, msg->rx_len); in dsi_long_read_resp()
1328 return msg->rx_len; in dsi_long_read_resp()
1333 struct drm_device *dev = msm_host->dev; in dsi_dma_base_get_6g()
1334 struct msm_drm_private *priv = dev->dev_private; in dsi_dma_base_get_6g()
1337 return -EINVAL; in dsi_dma_base_get_6g()
1339 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, in dsi_dma_base_get_6g()
1340 priv->kms->aspace, dma_base); in dsi_dma_base_get_6g()
1346 return -EINVAL; in dsi_dma_base_get_v2()
1348 *dma_base = msm_host->tx_buf_paddr; in dsi_dma_base_get_v2()
1354 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in dsi_cmd_dma_tx()
1359 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); in dsi_cmd_dma_tx()
1365 reinit_completion(&msm_host->dma_comp); in dsi_cmd_dma_tx()
1370 msm_host->id, dma_base, len); in dsi_cmd_dma_tx()
1372 ret = wait_for_completion_timeout(&msm_host->dma_comp, in dsi_cmd_dma_tx()
1376 ret = -ETIMEDOUT; in dsi_cmd_dma_tx()
1393 int buf_offset = buf - msm_host->rx_buf; in dsi_cmd_dma_rx()
1410 * repeating bytes and then append the new parameters to the rx buffer. in dsi_cmd_dma_rx()
1418 bytes_shifted = read_cnt - 16; in dsi_cmd_dma_rx()
1419 repeated_bytes = buf_offset - bytes_shifted; in dsi_cmd_dma_rx()
1422 for (i = cnt - 1; i >= 0; i--) { in dsi_cmd_dma_rx()
1438 int bllp_len = msm_host->mode->hdisplay * in dsi_cmds2buf_tx()
1439 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; in dsi_cmds2buf_tx()
1444 __func__, msg->type); in dsi_cmds2buf_tx()
1457 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { in dsi_cmds2buf_tx()
1460 return -EINVAL; in dsi_cmds2buf_tx()
1466 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); in dsi_cmds2buf_tx()
1470 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); in dsi_cmds2buf_tx()
1471 return -EIO; in dsi_cmds2buf_tx()
1481 u32 status = msm_host->err_work_state; in dsi_err_worker()
1488 msm_host->err_work_state = 0; in dsi_err_worker()
1490 /* enable dsi error interrupt */ in dsi_err_worker()
1504 msm_host->err_work_state |= DSI_ERR_STATE_ACK; in dsi_ack_err_status()
1516 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; in dsi_timeout_status()
1532 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; in dsi_dln0_phy_err()
1545 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; in dsi_fifo_status()
1547 msm_host->err_work_state |= in dsi_fifo_status()
1560 msm_host->err_work_state |= in dsi_status()
1573 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; in dsi_clk_status()
1579 /* disable dsi error interrupt */ in dsi_error()
1589 queue_work(msm_host->workqueue, &msm_host->err_work); in dsi_error()
1598 if (!msm_host->ctrl_base) in dsi_host_irq()
1601 spin_lock_irqsave(&msm_host->intr_lock, flags); in dsi_host_irq()
1604 spin_unlock_irqrestore(&msm_host->intr_lock, flags); in dsi_host_irq()
1606 DBG("isr=0x%x, id=%d", isr, msm_host->id); in dsi_host_irq()
1612 complete(&msm_host->video_comp); in dsi_host_irq()
1615 complete(&msm_host->dma_comp); in dsi_host_irq()
1621 struct mipi_dsi_device *dsi) in dsi_host_attach() argument
1626 if (dsi->lanes > msm_host->num_data_lanes) in dsi_host_attach()
1627 return -EINVAL; in dsi_host_attach()
1629 msm_host->channel = dsi->channel; in dsi_host_attach()
1630 msm_host->lanes = dsi->lanes; in dsi_host_attach()
1631 msm_host->format = dsi->format; in dsi_host_attach()
1632 msm_host->mode_flags = dsi->mode_flags; in dsi_host_attach()
1633 if (dsi->dsc) in dsi_host_attach()
1634 msm_host->dsc = dsi->dsc; in dsi_host_attach()
1636 ret = dsi_dev_attach(msm_host->pdev); in dsi_host_attach()
1640 DBG("id=%d", msm_host->id); in dsi_host_attach()
1646 struct mipi_dsi_device *dsi) in dsi_host_detach() argument
1650 dsi_dev_detach(msm_host->pdev); in dsi_host_detach()
1652 DBG("id=%d", msm_host->id); in dsi_host_detach()
1663 if (!msg || !msm_host->power_on) in dsi_host_transfer()
1664 return -EINVAL; in dsi_host_transfer()
1666 mutex_lock(&msm_host->cmd_mutex); in dsi_host_transfer()
1667 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); in dsi_host_transfer()
1668 mutex_unlock(&msm_host->cmd_mutex); in dsi_host_transfer()
1683 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1699 struct device *dev = &msm_host->pdev->dev; in dsi_host_parse_lane_data()
1704 prop = of_find_property(ep, "data-lanes", &len); in dsi_host_parse_lane_data()
1709 msm_host->num_data_lanes = 4; in dsi_host_parse_lane_data()
1719 msm_host->num_data_lanes = num_lanes; in dsi_host_parse_lane_data()
1721 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, in dsi_host_parse_lane_data()
1729 * compare DT specified physical-logical lane mappings with the ones in dsi_host_parse_lane_data()
1737 * the data-lanes array we get from DT has a logical->physical in dsi_host_parse_lane_data()
1739 * supported configurations in a physical->logical mapping. in dsi_host_parse_lane_data()
1753 msm_host->dlane_swap = i; in dsi_host_parse_lane_data()
1758 return -EINVAL; in dsi_host_parse_lane_data()
1765 if (dsc->bits_per_pixel & 0xf) { in dsi_populate_dsc_params()
1766 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); in dsi_populate_dsc_params()
1767 return -EINVAL; in dsi_populate_dsc_params()
1770 if (dsc->bits_per_component != 8) { in dsi_populate_dsc_params()
1771 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); in dsi_populate_dsc_params()
1772 return -EOPNOTSUPP; in dsi_populate_dsc_params()
1775 dsc->simple_422 = 0; in dsi_populate_dsc_params()
1776 dsc->convert_rgb = 1; in dsi_populate_dsc_params()
1777 dsc->vbr_enable = 0; in dsi_populate_dsc_params()
1782 /* handle only bpp = bpc = 8, pre-SCR panels */ in dsi_populate_dsc_params()
1785 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); in dsi_populate_dsc_params()
1789 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); in dsi_populate_dsc_params()
1790 dsc->line_buf_depth = dsc->bits_per_component + 1; in dsi_populate_dsc_params()
1797 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); in dsi_host_parse_dt()
1798 struct device *dev = &msm_host->pdev->dev; in dsi_host_parse_dt()
1799 struct device_node *np = dev->of_node; in dsi_host_parse_dt()
1805 * Get the endpoint of the output port of the DSI host. In our case, in dsi_host_parse_dt()
1808 * nothing connected to the dsi output. in dsi_host_parse_dt()
1810 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); in dsi_host_parse_dt()
1820 ret = -EINVAL; in dsi_host_parse_dt()
1824 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); in dsi_host_parse_dt()
1825 if (ret && ret != -EINVAL) { in dsi_host_parse_dt()
1831 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); in dsi_host_parse_dt()
1834 if (of_property_read_bool(np, "syscon-sfpb")) { in dsi_host_parse_dt()
1835 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, in dsi_host_parse_dt()
1836 "syscon-sfpb"); in dsi_host_parse_dt()
1837 if (IS_ERR(msm_host->sfpb)) { in dsi_host_parse_dt()
1840 ret = PTR_ERR(msm_host->sfpb); in dsi_host_parse_dt()
1852 struct platform_device *pdev = msm_host->pdev; in dsi_host_get_id()
1853 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; in dsi_host_get_id()
1859 return -EINVAL; in dsi_host_get_id()
1863 if (cfg->io_start[i][j] == res->start) in dsi_host_get_id()
1866 return -EINVAL; in dsi_host_get_id()
1872 struct platform_device *pdev = msm_dsi->pdev; in msm_dsi_host_init()
1876 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); in msm_dsi_host_init()
1878 return -ENOMEM; in msm_dsi_host_init()
1881 msm_host->pdev = pdev; in msm_dsi_host_init()
1882 msm_dsi->host = &msm_host->base; in msm_dsi_host_init()
1890 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); in msm_dsi_host_init()
1891 if (IS_ERR(msm_host->ctrl_base)) { in msm_dsi_host_init()
1892 pr_err("%s: unable to map Dsi ctrl base\n", __func__); in msm_dsi_host_init()
1893 return PTR_ERR(msm_host->ctrl_base); in msm_dsi_host_init()
1896 pm_runtime_enable(&pdev->dev); in msm_dsi_host_init()
1898 msm_host->cfg_hnd = dsi_get_config(msm_host); in msm_dsi_host_init()
1899 if (!msm_host->cfg_hnd) { in msm_dsi_host_init()
1901 return -EINVAL; in msm_dsi_host_init()
1903 cfg = msm_host->cfg_hnd->cfg; in msm_dsi_host_init()
1905 msm_host->id = dsi_host_get_id(msm_host); in msm_dsi_host_init()
1906 if (msm_host->id < 0) { in msm_dsi_host_init()
1907 pr_err("%s: unable to identify DSI host index\n", __func__); in msm_dsi_host_init()
1908 return msm_host->id; in msm_dsi_host_init()
1912 msm_host->ctrl_base += cfg->io_offset; in msm_dsi_host_init()
1914 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, in msm_dsi_host_init()
1915 cfg->regulator_data, in msm_dsi_host_init()
1916 &msm_host->supplies); in msm_dsi_host_init()
1922 pr_err("%s: unable to initialize dsi clks\n", __func__); in msm_dsi_host_init()
1926 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); in msm_dsi_host_init()
1927 if (!msm_host->rx_buf) { in msm_dsi_host_init()
1928 pr_err("%s: alloc rx temp buf failed\n", __func__); in msm_dsi_host_init()
1929 return -ENOMEM; in msm_dsi_host_init()
1932 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); in msm_dsi_host_init()
1936 ret = devm_pm_opp_of_add_table(&pdev->dev); in msm_dsi_host_init()
1937 if (ret && ret != -ENODEV) { in msm_dsi_host_init()
1938 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in msm_dsi_host_init()
1942 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in msm_dsi_host_init()
1943 if (!msm_host->irq) { in msm_dsi_host_init()
1944 dev_err(&pdev->dev, "failed to get irq\n"); in msm_dsi_host_init()
1945 return -EINVAL; in msm_dsi_host_init()
1949 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, in msm_dsi_host_init()
1953 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", in msm_dsi_host_init()
1954 msm_host->irq, ret); in msm_dsi_host_init()
1958 init_completion(&msm_host->dma_comp); in msm_dsi_host_init()
1959 init_completion(&msm_host->video_comp); in msm_dsi_host_init()
1960 mutex_init(&msm_host->dev_mutex); in msm_dsi_host_init()
1961 mutex_init(&msm_host->cmd_mutex); in msm_dsi_host_init()
1962 spin_lock_init(&msm_host->intr_lock); in msm_dsi_host_init()
1965 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); in msm_dsi_host_init()
1966 if (!msm_host->workqueue) in msm_dsi_host_init()
1967 return -ENOMEM; in msm_dsi_host_init()
1969 INIT_WORK(&msm_host->err_work, dsi_err_worker); in msm_dsi_host_init()
1971 msm_dsi->id = msm_host->id; in msm_dsi_host_init()
1973 DBG("Dsi Host %d initialized", msm_host->id); in msm_dsi_host_init()
1982 if (msm_host->workqueue) { in msm_dsi_host_destroy()
1983 destroy_workqueue(msm_host->workqueue); in msm_dsi_host_destroy()
1984 msm_host->workqueue = NULL; in msm_dsi_host_destroy()
1987 mutex_destroy(&msm_host->cmd_mutex); in msm_dsi_host_destroy()
1988 mutex_destroy(&msm_host->dev_mutex); in msm_dsi_host_destroy()
1990 pm_runtime_disable(&msm_host->pdev->dev); in msm_dsi_host_destroy()
1997 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_modeset_init()
2000 msm_host->dev = dev; in msm_dsi_host_modeset_init()
2002 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); in msm_dsi_host_modeset_init()
2016 /* Register mipi dsi host */ in msm_dsi_host_register()
2017 if (!msm_host->registered) { in msm_dsi_host_register()
2018 host->dev = &msm_host->pdev->dev; in msm_dsi_host_register()
2019 host->ops = &dsi_host_ops; in msm_dsi_host_register()
2024 msm_host->registered = true; in msm_dsi_host_register()
2034 if (msm_host->registered) { in msm_dsi_host_unregister()
2036 host->dev = NULL; in msm_dsi_host_unregister()
2037 host->ops = NULL; in msm_dsi_host_unregister()
2038 msm_host->registered = false; in msm_dsi_host_unregister()
2046 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_xfer_prepare()
2056 * mdp clock need to be enabled to receive dsi interrupt in msm_dsi_host_xfer_prepare()
2058 pm_runtime_get_sync(&msm_host->pdev->dev); in msm_dsi_host_xfer_prepare()
2059 cfg_hnd->ops->link_clk_set_rate(msm_host); in msm_dsi_host_xfer_prepare()
2060 cfg_hnd->ops->link_clk_enable(msm_host); in msm_dsi_host_xfer_prepare()
2064 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) in msm_dsi_host_xfer_prepare()
2067 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); in msm_dsi_host_xfer_prepare()
2069 msm_host->dma_cmd_ctrl_restore | in msm_dsi_host_xfer_prepare()
2081 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_xfer_restore()
2084 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); in msm_dsi_host_xfer_restore()
2086 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) in msm_dsi_host_xfer_restore()
2091 cfg_hnd->ops->link_clk_disable(msm_host); in msm_dsi_host_xfer_restore()
2092 pm_runtime_put(&msm_host->pdev->dev); in msm_dsi_host_xfer_restore()
2107 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_cmd_rx()
2111 int rlen = msg->rx_len; in msm_dsi_host_cmd_rx()
2128 buf = msm_host->rx_buf; in msm_dsi_host_cmd_rx()
2133 .channel = msg->channel, in msm_dsi_host_cmd_rx()
2146 return -EINVAL; in msm_dsi_host_cmd_rx()
2149 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && in msm_dsi_host_cmd_rx()
2150 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { in msm_dsi_host_cmd_rx()
2163 } else if (ret < msg->tx_len) { in msm_dsi_host_cmd_rx()
2165 return -ECOMM; in msm_dsi_host_cmd_rx()
2172 * since rx fifo is 16 bytes, dcs header is kept at first loop, in msm_dsi_host_cmd_rx()
2184 diff = data_byte - rlen; in msm_dsi_host_cmd_rx()
2188 rlen -= data_byte; in msm_dsi_host_cmd_rx()
2192 dlen -= 2; /* 2 crc */ in msm_dsi_host_cmd_rx()
2193 dlen -= diff; in msm_dsi_host_cmd_rx()
2206 * we need to shift the start position of rx in msm_dsi_host_cmd_rx()
2211 buf = msm_host->rx_buf + (10 - rlen); in msm_dsi_host_cmd_rx()
2213 buf = msm_host->rx_buf; in msm_dsi_host_cmd_rx()
2218 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); in msm_dsi_host_cmd_rx()
2259 msm_host->cphy_mode = src_phy->cphy_mode; in msm_dsi_host_set_phy_mode()
2280 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_get_phy_clk_req()
2283 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); in msm_dsi_host_get_phy_clk_req()
2290 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), in msm_dsi_host_get_phy_clk_req()
2293 if (msm_host->cphy_mode) in msm_dsi_host_get_phy_clk_req()
2294 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; in msm_dsi_host_get_phy_clk_req()
2296 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; in msm_dsi_host_get_phy_clk_req()
2297 clk_req->escclk_rate = msm_host->esc_clk_rate; in msm_dsi_host_get_phy_clk_req()
2304 enable_irq(msm_host->irq); in msm_dsi_host_enable_irq()
2311 disable_irq(msm_host->irq); in msm_dsi_host_disable_irq()
2319 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); in msm_dsi_host_enable()
2325 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { in msm_dsi_host_enable()
2327 * pm_runtime_put(&msm_host->pdev->dev); in msm_dsi_host_enable()
2330 msm_host->enabled = true; in msm_dsi_host_enable()
2338 msm_host->enabled = false; in msm_dsi_host_disable()
2340 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); in msm_dsi_host_disable()
2355 if (!msm_host->sfpb) in msm_dsi_sfpb_config()
2360 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, in msm_dsi_sfpb_config()
2370 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_power_on()
2373 mutex_lock(&msm_host->dev_mutex); in msm_dsi_host_power_on()
2374 if (msm_host->power_on) { in msm_dsi_host_power_on()
2375 DBG("dsi host already on"); in msm_dsi_host_power_on()
2379 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; in msm_dsi_host_power_on()
2380 if (phy_shared_timings->byte_intf_clk_div_2) in msm_dsi_host_power_on()
2381 msm_host->byte_intf_clk_rate /= 2; in msm_dsi_host_power_on()
2385 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, in msm_dsi_host_power_on()
2386 msm_host->supplies); in msm_dsi_host_power_on()
2393 pm_runtime_get_sync(&msm_host->pdev->dev); in msm_dsi_host_power_on()
2394 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); in msm_dsi_host_power_on()
2396 ret = cfg_hnd->ops->link_clk_enable(msm_host); in msm_dsi_host_power_on()
2403 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); in msm_dsi_host_power_on()
2414 msm_host->power_on = true; in msm_dsi_host_power_on()
2415 mutex_unlock(&msm_host->dev_mutex); in msm_dsi_host_power_on()
2420 cfg_hnd->ops->link_clk_disable(msm_host); in msm_dsi_host_power_on()
2421 pm_runtime_put(&msm_host->pdev->dev); in msm_dsi_host_power_on()
2423 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, in msm_dsi_host_power_on()
2424 msm_host->supplies); in msm_dsi_host_power_on()
2426 mutex_unlock(&msm_host->dev_mutex); in msm_dsi_host_power_on()
2433 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; in msm_dsi_host_power_off()
2435 mutex_lock(&msm_host->dev_mutex); in msm_dsi_host_power_off()
2436 if (!msm_host->power_on) { in msm_dsi_host_power_off()
2437 DBG("dsi host already off"); in msm_dsi_host_power_off()
2443 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); in msm_dsi_host_power_off()
2445 cfg_hnd->ops->link_clk_disable(msm_host); in msm_dsi_host_power_off()
2446 pm_runtime_put(&msm_host->pdev->dev); in msm_dsi_host_power_off()
2448 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, in msm_dsi_host_power_off()
2449 msm_host->supplies); in msm_dsi_host_power_off()
2453 DBG("-"); in msm_dsi_host_power_off()
2455 msm_host->power_on = false; in msm_dsi_host_power_off()
2458 mutex_unlock(&msm_host->dev_mutex); in msm_dsi_host_power_off()
2467 if (msm_host->mode) { in msm_dsi_host_set_display_mode()
2468 drm_mode_destroy(msm_host->dev, msm_host->mode); in msm_dsi_host_set_display_mode()
2469 msm_host->mode = NULL; in msm_dsi_host_set_display_mode()
2472 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); in msm_dsi_host_set_display_mode()
2473 if (!msm_host->mode) { in msm_dsi_host_set_display_mode()
2475 return -ENOMEM; in msm_dsi_host_set_display_mode()
2485 struct drm_dsc_config *dsc = msm_host->dsc; in msm_dsi_host_check_dsc()
2486 int pic_width = mode->hdisplay; in msm_dsi_host_check_dsc()
2487 int pic_height = mode->vdisplay; in msm_dsi_host_check_dsc()
2489 if (!msm_host->dsc) in msm_dsi_host_check_dsc()
2492 if (pic_width % dsc->slice_width) { in msm_dsi_host_check_dsc()
2493 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", in msm_dsi_host_check_dsc()
2494 pic_width, dsc->slice_width); in msm_dsi_host_check_dsc()
2498 if (pic_height % dsc->slice_height) { in msm_dsi_host_check_dsc()
2499 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", in msm_dsi_host_check_dsc()
2500 pic_height, dsc->slice_height); in msm_dsi_host_check_dsc()
2509 return to_msm_dsi_host(host)->mode_flags; in msm_dsi_host_get_mode_flags()
2516 pm_runtime_get_sync(&msm_host->pdev->dev); in msm_dsi_host_snapshot()
2518 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, in msm_dsi_host_snapshot()
2519 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); in msm_dsi_host_snapshot()
2521 pm_runtime_put_sync(&msm_host->pdev->dev); in msm_dsi_host_snapshot()
2534 /* use 24-bit RGB test pttern */ in msm_dsi_host_video_test_pattern_setup()
2567 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); in msm_dsi_host_test_pattern_en()
2589 return msm_host->dsc; in msm_dsi_host_get_dsc_config()