Lines Matching +full:sc8280xp +full:- +full:dpu
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
13 #include <linux/dma-buf.h>
62 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
65 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
72 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
75 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
76 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
80 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
81 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
84 pm_runtime_put_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
89 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, in _dpu_danger_signal_status()
111 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_read()
115 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); in _dpu_plane_danger_read()
124 drm_for_each_plane(plane, kms->dev) { in _dpu_plane_set_danger_state()
125 if (plane->fb && plane->state) { in _dpu_plane_set_danger_state()
128 plane->base.id, plane->fb->width, in _dpu_plane_set_danger_state()
129 plane->fb->height); in _dpu_plane_set_danger_state()
131 plane->state->src_x >> 16, in _dpu_plane_set_danger_state()
132 plane->state->src_y >> 16, in _dpu_plane_set_danger_state()
133 plane->state->src_w >> 16, in _dpu_plane_set_danger_state()
134 plane->state->src_h >> 16, in _dpu_plane_set_danger_state()
135 plane->state->crtc_x, plane->state->crtc_y, in _dpu_plane_set_danger_state()
136 plane->state->crtc_w, plane->state->crtc_h); in _dpu_plane_set_danger_state()
138 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); in _dpu_plane_set_danger_state()
146 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_write()
158 kms->has_danger_ctrl = false; in _dpu_plane_danger_write()
162 kms->has_danger_ctrl = true; in _dpu_plane_danger_write()
200 struct dpu_debugfs_regset32 *regset = s->private; in dpu_regset32_show()
201 struct dpu_kms *dpu_kms = regset->dpu_kms; in dpu_regset32_show()
205 if (!dpu_kms->mmio) in dpu_regset32_show()
208 base = dpu_kms->mmio + regset->offset; in dpu_regset32_show()
211 if (regset->offset & 0xF) { in dpu_regset32_show()
212 seq_printf(s, "[%x]", regset->offset & ~0xF); in dpu_regset32_show()
213 for (i = 0; i < (regset->offset & 0xF); i += 4) in dpu_regset32_show()
217 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
220 for (i = 0; i < regset->blk_len; i += 4) { in dpu_regset32_show()
221 addr = regset->offset + i; in dpu_regset32_show()
227 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
242 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); in dpu_debugfs_create_regset32()
247 regset->offset = round_down(offset, 4); in dpu_debugfs_create_regset32()
248 regset->blk_len = length; in dpu_debugfs_create_regset32()
249 regset->dpu_kms = dpu_kms; in dpu_debugfs_create_regset32()
263 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); in dpu_debugfs_sspp_init()
279 return -EINVAL; in dpu_kms_debugfs_init()
282 if (minor->type != DRM_MINOR_PRIMARY) in dpu_kms_debugfs_init()
285 entry = debugfs_create_dir("debug", minor->debugfs_root); in dpu_kms_debugfs_init()
308 return to_dpu_global_state(dpu_kms->global_state.state); in dpu_kms_get_existing_global_state()
317 struct msm_drm_private *priv = s->dev->dev_private; in dpu_kms_get_global_state()
318 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_get_global_state()
322 &dpu_kms->global_state); in dpu_kms_get_global_state()
334 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in dpu_kms_global_duplicate_state()
338 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in dpu_kms_global_duplicate_state()
340 return &state->base; in dpu_kms_global_duplicate_state()
371 return -ENOMEM; in dpu_kms_global_obj_init()
373 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, in dpu_kms_global_obj_init()
374 &state->base, in dpu_kms_global_obj_init()
377 state->rm = &dpu_kms->rm; in dpu_kms_global_obj_init()
384 drm_atomic_private_obj_fini(&dpu_kms->global_state); in dpu_kms_global_obj_fini()
391 struct device *dpu_dev = &dpu_kms->pdev->dev; in dpu_kms_parse_data_bus_icc_path()
393 path0 = msm_icc_get(dpu_dev, "mdp0-mem"); in dpu_kms_parse_data_bus_icc_path()
394 path1 = msm_icc_get(dpu_dev, "mdp1-mem"); in dpu_kms_parse_data_bus_icc_path()
399 dpu_kms->path[0] = path0; in dpu_kms_parse_data_bus_icc_path()
400 dpu_kms->num_paths = 1; in dpu_kms_parse_data_bus_icc_path()
403 dpu_kms->path[1] = path1; in dpu_kms_parse_data_bus_icc_path()
404 dpu_kms->num_paths++; in dpu_kms_parse_data_bus_icc_path()
422 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_enable_commit()
428 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_disable_commit()
436 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { in dpu_kms_flush_commit()
437 if (!crtc->state->active) in dpu_kms_flush_commit()
452 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_complete_commit()
465 if (!kms || !crtc || !crtc->state) { in dpu_kms_wait_for_commit_done()
470 dev = crtc->dev; in dpu_kms_wait_for_commit_done()
472 if (!crtc->state->enable) { in dpu_kms_wait_for_commit_done()
473 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
477 if (!drm_atomic_crtc_effectively_active(crtc->state)) { in dpu_kms_wait_for_commit_done()
478 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
482 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dpu_kms_wait_for_commit_done()
483 if (encoder->crtc != crtc) in dpu_kms_wait_for_commit_done()
486 * Wait for post-flush if necessary to delay before in dpu_kms_wait_for_commit_done()
488 * mode panels. This may be a no-op for command mode panels. in dpu_kms_wait_for_commit_done()
492 if (ret && ret != -EWOULDBLOCK) { in dpu_kms_wait_for_commit_done()
504 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_wait_flush()
530 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; in dpu_kms_dsi_set_te_source()
538 info->vsync_source = i; in dpu_kms_dsi_set_te_source()
543 return -EINVAL; in dpu_kms_dsi_set_te_source()
554 if (!(priv->dsi[0] || priv->dsi[1])) in _dpu_kms_initialize_dsi()
559 * - Single DSI host (dsi0 or dsi1) in _dpu_kms_initialize_dsi()
560 * - Two independent DSI hosts in _dpu_kms_initialize_dsi()
561 * - Bonded DSI0 and DSI1 hosts in _dpu_kms_initialize_dsi()
565 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { in _dpu_kms_initialize_dsi()
568 if (!priv->dsi[i]) in _dpu_kms_initialize_dsi()
571 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && in _dpu_kms_initialize_dsi()
572 !msm_dsi_is_master_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
579 if (msm_dsi_is_bonded_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
582 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); in _dpu_kms_initialize_dsi()
584 rc = dpu_kms_dsi_set_te_source(&info, priv->dsi[i]); in _dpu_kms_initialize_dsi()
596 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); in _dpu_kms_initialize_dsi()
603 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { in _dpu_kms_initialize_dsi()
604 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); in _dpu_kms_initialize_dsi()
626 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { in _dpu_kms_initialize_displayport()
627 if (!priv->dp[i]) in _dpu_kms_initialize_displayport()
641 yuv_supported = !!dpu_kms->catalog->cdm; in _dpu_kms_initialize_displayport()
642 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported); in _dpu_kms_initialize_displayport()
660 if (!priv->hdmi) in _dpu_kms_initialize_hdmi()
674 rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); in _dpu_kms_initialize_hdmi()
696 /* use only WB idx 2 instance for DPU */ in _dpu_kms_initialize_writeback()
700 maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; in _dpu_kms_initialize_writeback()
718 * _dpu_kms_setup_displays - create encoders, bridges and connectors
722 * @dpu_kms: Pointer to dpu kms structure
751 if (dpu_kms->catalog->wb_count) { in _dpu_kms_setup_displays()
752 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { in _dpu_kms_setup_displays()
753 if (dpu_kms->catalog->wb[i].id == WB_2) { in _dpu_kms_setup_displays()
755 dpu_kms->catalog->wb[i].format_list, in _dpu_kms_setup_displays()
756 dpu_kms->catalog->wb[i].num_formats); in _dpu_kms_setup_displays()
783 dev = dpu_kms->dev; in _dpu_kms_drm_obj_init()
784 priv = dev->dev_private; in _dpu_kms_drm_obj_init()
785 catalog = dpu_kms->catalog; in _dpu_kms_drm_obj_init()
799 max_crtc_count = min(catalog->mixer_count, num_encoders); in _dpu_kms_drm_obj_init()
802 for (i = 0; i < catalog->sspp_count; i++) { in _dpu_kms_drm_obj_init()
805 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) in _dpu_kms_drm_obj_init()
814 type, catalog->sspp[i].features, in _dpu_kms_drm_obj_init()
815 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); in _dpu_kms_drm_obj_init()
817 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, in _dpu_kms_drm_obj_init()
818 (1UL << max_crtc_count) - 1); in _dpu_kms_drm_obj_init()
840 priv->num_crtcs++; in _dpu_kms_drm_obj_init()
845 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; in _dpu_kms_drm_obj_init()
854 dpu_kms->hw_intr = NULL; in _dpu_kms_hw_destroy()
859 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { in _dpu_kms_hw_destroy()
860 dpu_kms->hw_vbif[i] = NULL; in _dpu_kms_hw_destroy()
865 dpu_kms->catalog = NULL; in _dpu_kms_hw_destroy()
867 dpu_kms->hw_mdp = NULL; in _dpu_kms_hw_destroy()
883 msm_kms_destroy(&dpu_kms->base); in dpu_kms_destroy()
885 if (dpu_kms->rpm_enabled) in dpu_kms_destroy()
886 pm_runtime_disable(&dpu_kms->pdev->dev); in dpu_kms_destroy()
894 if (!dpu_kms || !dpu_kms->dev) in dpu_irq_postinstall()
895 return -EINVAL; in dpu_irq_postinstall()
897 priv = dpu_kms->dev->dev_private; in dpu_irq_postinstall()
899 return -EINVAL; in dpu_irq_postinstall()
913 cat = dpu_kms->catalog; in dpu_kms_mdp_snapshot()
915 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
917 /* dump CTL sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
918 for (i = 0; i < cat->ctl_count; i++) in dpu_kms_mdp_snapshot()
919 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, in dpu_kms_mdp_snapshot()
920 dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name); in dpu_kms_mdp_snapshot()
922 /* dump DSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
923 for (i = 0; i < cat->dspp_count; i++) { in dpu_kms_mdp_snapshot()
924 base = dpu_kms->mmio + cat->dspp[i].base; in dpu_kms_mdp_snapshot()
925 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, cat->dspp[i].name); in dpu_kms_mdp_snapshot()
927 if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) in dpu_kms_mdp_snapshot()
928 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, in dpu_kms_mdp_snapshot()
929 base + cat->dspp[i].sblk->pcc.base, "%s_%s", in dpu_kms_mdp_snapshot()
930 cat->dspp[i].name, in dpu_kms_mdp_snapshot()
931 cat->dspp[i].sblk->pcc.name); in dpu_kms_mdp_snapshot()
934 /* dump INTF sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
935 for (i = 0; i < cat->intf_count; i++) in dpu_kms_mdp_snapshot()
936 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, in dpu_kms_mdp_snapshot()
937 dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name); in dpu_kms_mdp_snapshot()
939 /* dump PP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
940 for (i = 0; i < cat->pingpong_count; i++) { in dpu_kms_mdp_snapshot()
941 base = dpu_kms->mmio + cat->pingpong[i].base; in dpu_kms_mdp_snapshot()
942 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base, in dpu_kms_mdp_snapshot()
943 cat->pingpong[i].name); in dpu_kms_mdp_snapshot()
945 /* TE2 sub-block has length of 0, so will not print it */ in dpu_kms_mdp_snapshot()
947 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) in dpu_kms_mdp_snapshot()
948 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, in dpu_kms_mdp_snapshot()
949 base + cat->pingpong[i].sblk->dither.base, in dpu_kms_mdp_snapshot()
950 "%s_%s", cat->pingpong[i].name, in dpu_kms_mdp_snapshot()
951 cat->pingpong[i].sblk->dither.name); in dpu_kms_mdp_snapshot()
954 /* dump SSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
955 for (i = 0; i < cat->sspp_count; i++) { in dpu_kms_mdp_snapshot()
956 base = dpu_kms->mmio + cat->sspp[i].base; in dpu_kms_mdp_snapshot()
957 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, cat->sspp[i].name); in dpu_kms_mdp_snapshot()
959 if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) in dpu_kms_mdp_snapshot()
960 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, in dpu_kms_mdp_snapshot()
961 base + cat->sspp[i].sblk->scaler_blk.base, in dpu_kms_mdp_snapshot()
962 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
963 cat->sspp[i].sblk->scaler_blk.name); in dpu_kms_mdp_snapshot()
965 if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) in dpu_kms_mdp_snapshot()
966 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, in dpu_kms_mdp_snapshot()
967 base + cat->sspp[i].sblk->csc_blk.base, in dpu_kms_mdp_snapshot()
968 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
969 cat->sspp[i].sblk->csc_blk.name); in dpu_kms_mdp_snapshot()
972 /* dump LM sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
973 for (i = 0; i < cat->mixer_count; i++) in dpu_kms_mdp_snapshot()
974 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, in dpu_kms_mdp_snapshot()
975 dpu_kms->mmio + cat->mixer[i].base, cat->mixer[i].name); in dpu_kms_mdp_snapshot()
977 /* dump WB sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
978 for (i = 0; i < cat->wb_count; i++) in dpu_kms_mdp_snapshot()
979 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, in dpu_kms_mdp_snapshot()
980 dpu_kms->mmio + cat->wb[i].base, cat->wb[i].name); in dpu_kms_mdp_snapshot()
982 if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { in dpu_kms_mdp_snapshot()
984 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
985 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, in dpu_kms_mdp_snapshot()
986 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); in dpu_kms_mdp_snapshot()
988 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, in dpu_kms_mdp_snapshot()
989 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
992 /* dump DSC sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
993 for (i = 0; i < cat->dsc_count; i++) { in dpu_kms_mdp_snapshot()
994 base = dpu_kms->mmio + cat->dsc[i].base; in dpu_kms_mdp_snapshot()
995 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, cat->dsc[i].name); in dpu_kms_mdp_snapshot()
997 if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { in dpu_kms_mdp_snapshot()
998 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; in dpu_kms_mdp_snapshot()
999 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; in dpu_kms_mdp_snapshot()
1002 cat->dsc[i].name, enc.name); in dpu_kms_mdp_snapshot()
1004 cat->dsc[i].name, ctl.name); in dpu_kms_mdp_snapshot()
1008 if (cat->cdm) in dpu_kms_mdp_snapshot()
1009 msm_disp_snapshot_add_block(disp_state, cat->cdm->len, in dpu_kms_mdp_snapshot()
1010 dpu_kms->mmio + cat->cdm->base, cat->cdm->name); in dpu_kms_mdp_snapshot()
1012 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
1040 if (!dpu_kms->base.aspace) in _dpu_kms_mmu_destroy()
1043 mmu = dpu_kms->base.aspace->mmu; in _dpu_kms_mmu_destroy()
1045 mmu->funcs->detach(mmu); in _dpu_kms_mmu_destroy()
1046 msm_gem_address_space_put(dpu_kms->base.aspace); in _dpu_kms_mmu_destroy()
1048 dpu_kms->base.aspace = NULL; in _dpu_kms_mmu_destroy()
1055 aspace = msm_kms_init_aspace(dpu_kms->dev); in _dpu_kms_mmu_init()
1059 dpu_kms->base.aspace = aspace; in _dpu_kms_mmu_init()
1068 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); in dpu_kms_get_clk_rate()
1081 int i, rc = -EINVAL; in dpu_kms_hw_init()
1091 dev = dpu_kms->dev; in dpu_kms_hw_init()
1093 dev->mode_config.cursor_width = 512; in dpu_kms_hw_init()
1094 dev->mode_config.cursor_height = 512; in dpu_kms_hw_init()
1100 atomic_set(&dpu_kms->bandwidth_ref, 0); in dpu_kms_hw_init()
1102 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1106 core_rev = readl_relaxed(dpu_kms->mmio + 0x0); in dpu_kms_hw_init()
1108 pr_info("dpu hardware revision:0x%x\n", core_rev); in dpu_kms_hw_init()
1110 dpu_kms->catalog = of_device_get_match_data(dev->dev); in dpu_kms_hw_init()
1111 if (!dpu_kms->catalog) { in dpu_kms_hw_init()
1113 rc = -EINVAL; in dpu_kms_hw_init()
1127 dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); in dpu_kms_hw_init()
1128 if (IS_ERR(dpu_kms->mdss)) { in dpu_kms_hw_init()
1129 rc = PTR_ERR(dpu_kms->mdss); in dpu_kms_hw_init()
1134 if (!dpu_kms->mdss) { in dpu_kms_hw_init()
1135 rc = -EINVAL; in dpu_kms_hw_init()
1140 rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio); in dpu_kms_hw_init()
1146 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev, in dpu_kms_hw_init()
1147 dpu_kms->catalog->mdp, in dpu_kms_hw_init()
1148 dpu_kms->mmio, in dpu_kms_hw_init()
1149 dpu_kms->catalog->mdss_ver); in dpu_kms_hw_init()
1150 if (IS_ERR(dpu_kms->hw_mdp)) { in dpu_kms_hw_init()
1151 rc = PTR_ERR(dpu_kms->hw_mdp); in dpu_kms_hw_init()
1153 dpu_kms->hw_mdp = NULL; in dpu_kms_hw_init()
1157 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { in dpu_kms_hw_init()
1159 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; in dpu_kms_hw_init()
1161 hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]); in dpu_kms_hw_init()
1164 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc); in dpu_kms_hw_init()
1168 dpu_kms->hw_vbif[vbif->id] = hw; in dpu_kms_hw_init()
1178 rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate); in dpu_kms_hw_init()
1185 * We need to program DP <-> PHY relationship only for SC8180X since it in dpu_kms_hw_init()
1188 * the INTF <->DP relationship isn't static anymore, this needs to be in dpu_kms_hw_init()
1191 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu")) in dpu_kms_hw_init()
1192 dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, }); in dpu_kms_hw_init()
1194 dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog); in dpu_kms_hw_init()
1195 if (IS_ERR(dpu_kms->hw_intr)) { in dpu_kms_hw_init()
1196 rc = PTR_ERR(dpu_kms->hw_intr); in dpu_kms_hw_init()
1198 dpu_kms->hw_intr = NULL; in dpu_kms_hw_init()
1202 dev->mode_config.min_width = 0; in dpu_kms_hw_init()
1203 dev->mode_config.min_height = 0; in dpu_kms_hw_init()
1209 dev->mode_config.max_width = in dpu_kms_hw_init()
1210 dpu_kms->catalog->caps->max_mixer_width * 2; in dpu_kms_hw_init()
1211 dev->mode_config.max_height = 4096; in dpu_kms_hw_init()
1213 dev->max_vblank_count = 0xffffffff; in dpu_kms_hw_init()
1214 /* Disable vblank irqs aggressively for power-saving */ in dpu_kms_hw_init()
1215 dev->vblank_disable_immediate = true; in dpu_kms_hw_init()
1229 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1234 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1243 struct msm_drm_private *priv = ddev->dev_private; in dpu_kms_init()
1244 struct device *dev = ddev->dev; in dpu_kms_init()
1246 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_init()
1257 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); in dpu_kms_init()
1262 dpu_kms->dev = ddev; in dpu_kms_init()
1264 pm_runtime_enable(&pdev->dev); in dpu_kms_init()
1265 dpu_kms->rpm_enabled = true; in dpu_kms_init()
1272 struct platform_device *pdev = dpu_kms->pdev; in dpu_kms_mmap_mdp5()
1276 if (!dev_is_platform(dpu_kms->pdev->dev.parent)) in dpu_kms_mmap_mdp5()
1277 return -EINVAL; in dpu_kms_mmap_mdp5()
1279 mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent); in dpu_kms_mmap_mdp5()
1281 dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys"); in dpu_kms_mmap_mdp5()
1282 if (IS_ERR(dpu_kms->mmio)) { in dpu_kms_mmap_mdp5()
1283 ret = PTR_ERR(dpu_kms->mmio); in dpu_kms_mmap_mdp5()
1285 dpu_kms->mmio = NULL; in dpu_kms_mmap_mdp5()
1288 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); in dpu_kms_mmap_mdp5()
1290 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, in dpu_kms_mmap_mdp5()
1291 dpu_kms->pdev, in dpu_kms_mmap_mdp5()
1293 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { in dpu_kms_mmap_mdp5()
1294 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); in dpu_kms_mmap_mdp5()
1296 dpu_kms->vbif[VBIF_RT] = NULL; in dpu_kms_mmap_mdp5()
1300 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev, in dpu_kms_mmap_mdp5()
1301 dpu_kms->pdev, in dpu_kms_mmap_mdp5()
1303 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { in dpu_kms_mmap_mdp5()
1304 dpu_kms->vbif[VBIF_NRT] = NULL; in dpu_kms_mmap_mdp5()
1313 struct platform_device *pdev = dpu_kms->pdev; in dpu_kms_mmap_dpu()
1316 dpu_kms->mmio = msm_ioremap(pdev, "mdp"); in dpu_kms_mmap_dpu()
1317 if (IS_ERR(dpu_kms->mmio)) { in dpu_kms_mmap_dpu()
1318 ret = PTR_ERR(dpu_kms->mmio); in dpu_kms_mmap_dpu()
1320 dpu_kms->mmio = NULL; in dpu_kms_mmap_dpu()
1323 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); in dpu_kms_mmap_dpu()
1325 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); in dpu_kms_mmap_dpu()
1326 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { in dpu_kms_mmap_dpu()
1327 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); in dpu_kms_mmap_dpu()
1329 dpu_kms->vbif[VBIF_RT] = NULL; in dpu_kms_mmap_dpu()
1333 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); in dpu_kms_mmap_dpu()
1334 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { in dpu_kms_mmap_dpu()
1335 dpu_kms->vbif[VBIF_NRT] = NULL; in dpu_kms_mmap_dpu()
1344 struct device *dev = &pdev->dev; in dpu_dev_probe()
1349 if (!msm_disp_drv_should_bind(&pdev->dev, true)) in dpu_dev_probe()
1350 return -ENODEV; in dpu_dev_probe()
1354 return -ENOMEM; in dpu_dev_probe()
1356 dpu_kms->pdev = pdev; in dpu_dev_probe()
1363 if (ret && ret != -ENODEV) in dpu_dev_probe()
1366 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); in dpu_dev_probe()
1370 dpu_kms->num_clocks = ret; in dpu_dev_probe()
1376 dpu_kms->base.irq = irq; in dpu_dev_probe()
1378 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5")) in dpu_dev_probe()
1389 return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base); in dpu_dev_probe()
1394 component_master_del(&pdev->dev, &msm_drm_ops); in dpu_dev_remove()
1402 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_suspend()
1406 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_suspend()
1408 for (i = 0; i < dpu_kms->num_paths; i++) in dpu_runtime_suspend()
1409 icc_set_bw(dpu_kms->path[i], 0, 0); in dpu_runtime_suspend()
1416 int rc = -1; in dpu_runtime_resume()
1419 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_resume()
1423 ddev = dpu_kms->dev; in dpu_runtime_resume()
1425 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_resume()
1448 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1449 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1450 { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
1451 { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
1452 { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1453 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1454 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1455 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1456 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1457 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1458 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1459 { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
1460 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1461 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1462 { .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
1463 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1464 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1465 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1466 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1467 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1468 { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
1469 { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },