79 		struct dpu_hw_tear_check *te)  in dpu_hw_pp_enable_te()  argument
84 	if (!pp || !te)  in dpu_hw_pp_enable_te()
89 	if (te->hw_vsync_mode)  in dpu_hw_pp_enable_te()
92 	cfg |= te->vsync_count;  in dpu_hw_pp_enable_te()
95 	DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);  in dpu_hw_pp_enable_te()
96 	DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);  in dpu_hw_pp_enable_te()
97 	DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);  in dpu_hw_pp_enable_te()
98 	DPU_REG_WRITE(c, PP_START_POS, te->start_pos);  in dpu_hw_pp_enable_te()
100 			((te->sync_threshold_continue << 16) |  in dpu_hw_pp_enable_te()
101 			 te->sync_threshold_start));  in dpu_hw_pp_enable_te()
103 			(te->start_pos + te->sync_threshold_start + 1));  in dpu_hw_pp_enable_te()