22 #define MDP_INTF_OFF(intf)				(0x6A000 + 0x800 * (intf))
23 #define MDP_INTF_INTR_EN(intf)				(MDP_INTF_OFF(intf) + 0x1c0)
24 #define MDP_INTF_INTR_STATUS(intf)			(MDP_INTF_OFF(intf) + 0x1c4)
25 #define MDP_INTF_INTR_CLEAR(intf)			(MDP_INTF_OFF(intf) + 0x1c8)
26 #define MDP_INTF_TEAR_OFF(intf)				(0x6D700 + 0x100 * (intf))
27 #define MDP_INTF_INTR_TEAR_EN(intf)			(MDP_INTF_TEAR_OFF(intf) + 0x000)
28 #define MDP_INTF_INTR_TEAR_STATUS(intf)			(MDP_INTF_TEAR_OFF(intf) + 0x004)
29 #define MDP_INTF_INTR_TEAR_CLEAR(intf)			(MDP_INTF_TEAR_OFF(intf) + 0x008)
30 #define MDP_AD4_OFF(ad4)				(0x7C000 + 0x1000 * (ad4))
31 #define MDP_AD4_INTR_EN_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x41c)
32 #define MDP_AD4_INTR_CLEAR_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x424)
33 #define MDP_AD4_INTR_STATUS_OFF(ad4)			(MDP_AD4_OFF(ad4) + 0x420)
34 #define MDP_INTF_REV_7xxx_OFF(intf)			(0x34000 + 0x1000 * (intf))
35 #define MDP_INTF_REV_7xxx_INTR_EN(intf)			(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c0)
36 #define MDP_INTF_REV_7xxx_INTR_STATUS(intf)		(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c4)
37 #define MDP_INTF_REV_7xxx_INTR_CLEAR(intf)		(MDP_INTF_REV_7xxx_OFF(intf) + 0x1c8)
38 #define MDP_INTF_REV_7xxx_TEAR_OFF(intf)		(0x34800 + 0x1000 * (intf))
39 #define MDP_INTF_REV_7xxx_INTR_TEAR_EN(intf)		(MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x000)
40 #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf)	(MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
41 #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf)		(MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
75 		MDP_INTF_INTR_CLEAR(0),
76 		MDP_INTF_INTR_EN(0),
77 		MDP_INTF_INTR_STATUS(0)
115 		MDP_AD4_INTR_CLEAR_OFF(0),
116 		MDP_AD4_INTR_EN_OFF(0),
117 		MDP_AD4_INTR_STATUS_OFF(0),
146 		MDP_INTF_REV_7xxx_INTR_CLEAR(0),
147 		MDP_INTF_REV_7xxx_INTR_EN(0),
148 		MDP_INTF_REV_7xxx_INTR_STATUS(0)
255 	for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {  in dpu_core_irq()
279 		while ((bit = ffs(irq_status)) != 0) {  in dpu_core_irq()
350 	pr_debug("DPU IRQ=[%d, %d] %senabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n",  in dpu_hw_intr_enable_irq_locked()
354 	return 0;  in dpu_hw_intr_enable_irq_locked()
385 	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {  in dpu_hw_intr_disable_irq_locked()
402 	pr_debug("DPU IRQ=[%d, %d] %sdisabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n",  in dpu_hw_intr_disable_irq_locked()
406 	return 0;  in dpu_hw_intr_disable_irq_locked()
417 	for (i = 0; i < MDP_INTR_MAX; i++) {  in dpu_clear_irqs()
420 					intr->intr_set[i].clr_off, 0xffffffff);  in dpu_clear_irqs()
435 	for (i = 0; i < MDP_INTR_MAX; i++) {  in dpu_disable_all_irqs()
438 					intr->intr_set[i].en_off, 0x00000000);  in dpu_disable_all_irqs()
454 		return 0;  in dpu_core_irq_read()
458 		return 0;  in dpu_core_irq_read()
498 	intr->hw.blk_addr = addr + m->mdp[0].base;  in dpu_hw_intr_init()
503 	for (i = 0; i < m->intf_count; i++) {  in dpu_hw_intr_init()
541 	VERB("[%pS] IRQ=[%d, %d]\n", __builtin_return_address(0),  in dpu_core_irq_register_callback()
567 	return 0;  in dpu_core_irq_register_callback()
583 	VERB("[%pS] IRQ=[%d, %d]\n", __builtin_return_address(0),  in dpu_core_irq_unregister_callback()
602 	return 0;  in dpu_core_irq_unregister_callback()
626 	return 0;  in dpu_debugfs_core_irq_show()
652 		atomic_set(&irq_entry->count, 0);  in dpu_core_irq_preinstall()