Lines Matching refs:phys_enc
220 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) in dpu_encoder_get_drm_fmt() argument
227 drm_enc = phys_enc->parent; in dpu_encoder_get_drm_fmt()
230 mode = &phys_enc->cached_mode; in dpu_encoder_get_drm_fmt()
238 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) in dpu_encoder_needs_periph_flush() argument
246 drm_enc = phys_enc->parent; in dpu_encoder_needs_periph_flush()
250 mode = &phys_enc->cached_mode; in dpu_encoder_needs_periph_flush()
252 return phys_enc->hw_intf->cap->type == INTF_DP && in dpu_encoder_needs_periph_flush()
388 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
392 DRMID(phys_enc->parent), in dpu_encoder_helper_report_irq_timeout()
393 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), in dpu_encoder_helper_report_irq_timeout()
394 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_helper_report_irq_timeout()
395 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, in dpu_encoder_helper_report_irq_timeout()
396 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); in dpu_encoder_helper_report_irq_timeout()
398 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, in dpu_encoder_helper_report_irq_timeout()
405 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_wait_for_irq() argument
420 if (phys_enc->enable_state == DPU_ENC_DISABLED) { in dpu_encoder_helper_wait_for_irq()
422 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
429 DRMID(phys_enc->parent), func); in dpu_encoder_helper_wait_for_irq()
434 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
435 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
439 DRMID(phys_enc->parent), in dpu_encoder_helper_wait_for_irq()
444 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); in dpu_encoder_helper_wait_for_irq()
450 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
451 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
454 func(phys_enc); in dpu_encoder_helper_wait_for_irq()
461 DRMID(phys_enc->parent), func, in dpu_encoder_helper_wait_for_irq()
462 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
467 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), in dpu_encoder_helper_wait_for_irq()
469 phys_enc->hw_pp->idx - PINGPONG_0, in dpu_encoder_helper_wait_for_irq()
499 struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_split_config() argument
507 if (!phys_enc->hw_mdptop || !phys_enc->parent) { in dpu_encoder_helper_split_config()
508 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); in dpu_encoder_helper_split_config()
512 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_split_config()
513 hw_mdptop = phys_enc->hw_mdptop; in dpu_encoder_helper_split_config()
525 if (phys_enc->split_role == ENC_ROLE_SOLO) { in dpu_encoder_helper_split_config()
532 cfg.mode = phys_enc->intf_mode; in dpu_encoder_helper_split_config()
535 if (cfg.en && phys_enc->ops.needs_single_flush && in dpu_encoder_helper_split_config()
536 phys_enc->ops.needs_single_flush(phys_enc)) in dpu_encoder_helper_split_config()
539 if (phys_enc->split_role == ENC_ROLE_MASTER) { in dpu_encoder_helper_split_config()
747 struct dpu_encoder_phys *phys_enc; in _dpu_encoder_update_vsync_source() local
784 phys_enc = dpu_enc->phys_encs[i]; in _dpu_encoder_update_vsync_source()
786 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) in _dpu_encoder_update_vsync_source()
787 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, in _dpu_encoder_update_vsync_source()
1590 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_trigger_start() argument
1594 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1597 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); in dpu_encoder_helper_trigger_start()
1628 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_hw_reset() argument
1635 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_hw_reset()
1636 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
1637 drm_enc = phys_enc->parent; in dpu_encoder_helper_hw_reset()
1651 phys_enc->enable_state = DPU_ENC_ENABLED; in dpu_encoder_helper_hw_reset()
2022 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_reset_mixers() argument
2029 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; in dpu_encoder_helper_reset_mixers()
2034 if (phys_enc->hw_ctl->ops.clear_all_blendstages) in dpu_encoder_helper_reset_mixers()
2035 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl); in dpu_encoder_helper_reset_mixers()
2037 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); in dpu_encoder_helper_reset_mixers()
2039 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, in dpu_encoder_helper_reset_mixers()
2040 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); in dpu_encoder_helper_reset_mixers()
2044 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer) in dpu_encoder_helper_reset_mixers()
2045 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); in dpu_encoder_helper_reset_mixers()
2048 if (phys_enc->hw_ctl->ops.setup_blendstage) in dpu_encoder_helper_reset_mixers()
2049 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); in dpu_encoder_helper_reset_mixers()
2088 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_phys_cleanup() argument
2090 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; in dpu_encoder_helper_phys_cleanup()
2095 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); in dpu_encoder_helper_phys_cleanup()
2097 phys_enc->hw_ctl->ops.reset(ctl); in dpu_encoder_helper_phys_cleanup()
2099 dpu_encoder_helper_reset_mixers(phys_enc); in dpu_encoder_helper_phys_cleanup()
2106 if (phys_enc->hw_wb) { in dpu_encoder_helper_phys_cleanup()
2108 if (phys_enc->hw_wb->ops.bind_pingpong_blk) in dpu_encoder_helper_phys_cleanup()
2109 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); in dpu_encoder_helper_phys_cleanup()
2112 if (phys_enc->hw_ctl->ops.update_pending_flush_wb) in dpu_encoder_helper_phys_cleanup()
2113 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); in dpu_encoder_helper_phys_cleanup()
2116 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) in dpu_encoder_helper_phys_cleanup()
2117 phys_enc->hw_intf->ops.bind_pingpong_blk( in dpu_encoder_helper_phys_cleanup()
2122 if (phys_enc->hw_ctl->ops.update_pending_flush_intf) in dpu_encoder_helper_phys_cleanup()
2123 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl, in dpu_encoder_helper_phys_cleanup()
2129 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { in dpu_encoder_helper_phys_cleanup()
2130 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, in dpu_encoder_helper_phys_cleanup()
2132 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d) in dpu_encoder_helper_phys_cleanup()
2133 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl, in dpu_encoder_helper_phys_cleanup()
2134 phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_helper_phys_cleanup()
2137 if (phys_enc->hw_cdm) { in dpu_encoder_helper_phys_cleanup()
2138 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) in dpu_encoder_helper_phys_cleanup()
2139 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, in dpu_encoder_helper_phys_cleanup()
2141 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm) in dpu_encoder_helper_phys_cleanup()
2142 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl, in dpu_encoder_helper_phys_cleanup()
2143 phys_enc->hw_cdm->idx); in dpu_encoder_helper_phys_cleanup()
2152 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_helper_phys_cleanup()
2153 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_helper_phys_cleanup()
2155 if (phys_enc->hw_intf) in dpu_encoder_helper_phys_cleanup()
2156 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_helper_phys_cleanup()
2157 if (phys_enc->hw_wb) in dpu_encoder_helper_phys_cleanup()
2158 intf_cfg.wb = phys_enc->hw_wb->idx; in dpu_encoder_helper_phys_cleanup()
2160 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) in dpu_encoder_helper_phys_cleanup()
2161 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_helper_phys_cleanup()
2171 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_phys_setup_cdm() argument
2180 if (!phys_enc) in dpu_encoder_helper_phys_setup_cdm()
2183 cdm_cfg = &phys_enc->cdm_cfg; in dpu_encoder_helper_phys_setup_cdm()
2184 hw_pp = phys_enc->hw_pp; in dpu_encoder_helper_phys_setup_cdm()
2185 hw_cdm = phys_enc->hw_cdm; in dpu_encoder_helper_phys_setup_cdm()
2191 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), in dpu_encoder_helper_phys_setup_cdm()
2201 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; in dpu_encoder_helper_phys_setup_cdm()
2202 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; in dpu_encoder_helper_phys_setup_cdm()
2226 DRMID(phys_enc->parent)); in dpu_encoder_helper_phys_setup_cdm()
2233 DRMID(phys_enc->parent), cdm_cfg->output_width, in dpu_encoder_helper_phys_setup_cdm()
2243 DRMID(phys_enc->parent), ret); in dpu_encoder_helper_phys_setup_cdm()
2615 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) in dpu_encoder_helper_get_dsc() argument
2617 struct drm_encoder *encoder = phys_enc->parent; in dpu_encoder_helper_get_dsc()
2623 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, in dpu_encoder_phys_init() argument
2626 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; in dpu_encoder_phys_init()
2627 phys_enc->hw_intf = p->hw_intf; in dpu_encoder_phys_init()
2628 phys_enc->hw_wb = p->hw_wb; in dpu_encoder_phys_init()
2629 phys_enc->parent = p->parent; in dpu_encoder_phys_init()
2630 phys_enc->dpu_kms = p->dpu_kms; in dpu_encoder_phys_init()
2631 phys_enc->split_role = p->split_role; in dpu_encoder_phys_init()
2632 phys_enc->enc_spinlock = p->enc_spinlock; in dpu_encoder_phys_init()
2633 phys_enc->enable_state = DPU_ENC_DISABLED; in dpu_encoder_phys_init()
2635 atomic_set(&phys_enc->pending_kickoff_cnt, 0); in dpu_encoder_phys_init()
2636 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); in dpu_encoder_phys_init()
2638 atomic_set(&phys_enc->vsync_cnt, 0); in dpu_encoder_phys_init()
2639 atomic_set(&phys_enc->underrun_cnt, 0); in dpu_encoder_phys_init()
2641 init_waitqueue_head(&phys_enc->pending_kickoff_wq); in dpu_encoder_phys_init()