2176 	struct dpu_hw_cdm_cfg *cdm_cfg;  in dpu_encoder_helper_phys_setup_cdm()  local
2183 	cdm_cfg = &phys_enc->cdm_cfg;  in dpu_encoder_helper_phys_setup_cdm()
2199 	memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));  in dpu_encoder_helper_phys_setup_cdm()
2201 	cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;  in dpu_encoder_helper_phys_setup_cdm()
2202 	cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;  in dpu_encoder_helper_phys_setup_cdm()
2203 	cdm_cfg->output_fmt = dpu_fmt;  in dpu_encoder_helper_phys_setup_cdm()
2204 	cdm_cfg->output_type = output_type;  in dpu_encoder_helper_phys_setup_cdm()
2205 	cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?  in dpu_encoder_helper_phys_setup_cdm()
2207 	cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;  in dpu_encoder_helper_phys_setup_cdm()
2210 	switch (cdm_cfg->output_fmt->chroma_sample) {  in dpu_encoder_helper_phys_setup_cdm()
2212 		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;  in dpu_encoder_helper_phys_setup_cdm()
2213 		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;  in dpu_encoder_helper_phys_setup_cdm()
2216 		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;  in dpu_encoder_helper_phys_setup_cdm()
2217 		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;  in dpu_encoder_helper_phys_setup_cdm()
2220 		cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;  in dpu_encoder_helper_phys_setup_cdm()
2221 		cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;  in dpu_encoder_helper_phys_setup_cdm()
2227 		cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;  in dpu_encoder_helper_phys_setup_cdm()
2228 		cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;  in dpu_encoder_helper_phys_setup_cdm()
2233 		  DRMID(phys_enc->parent), cdm_cfg->output_width,  in dpu_encoder_helper_phys_setup_cdm()
2234 		  cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,  in dpu_encoder_helper_phys_setup_cdm()
2235 		  cdm_cfg->output_type, cdm_cfg->output_bit_depth,  in dpu_encoder_helper_phys_setup_cdm()
2236 		  cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);  in dpu_encoder_helper_phys_setup_cdm()
2239 		cdm_cfg->pp_id = hw_pp->idx;  in dpu_encoder_helper_phys_setup_cdm()
2240 		ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);  in dpu_encoder_helper_phys_setup_cdm()