1 /* SPDX-License-Identifier: GPL-2.0-only */
33  * @enum adreno_family: identify generation and possibly sub-generation
35  * In some cases there are distinct sub-generations within a major revision
37  * necessary sub-generation.
90 	 * @chipids: Table of matching chip-ids
131  *      -----+---------
171 	 * of gpu firmware to linux-firmware, the fw files were
173 	 * android kernel.  But linux-firmware preferred they be
225 		 * Whether to use 4-channel macrotiling mode or the newer
226 		 * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
227 		 * 4-channel and 1 is 8-channel.
259 	int __ret = -ETIMEDOUT;                            \
276 	WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);  in adreno_patchid()
277 	return gpu->chip_id & 0xff;  in adreno_patchid()
282 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_revn()
284 	return gpu->info->revn == revn;  in adreno_is_revn()
289 	return gpu->gmu_is_wrapper;  in adreno_has_gmu_wrapper()
294 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a2xx()
296 	return gpu->info->family <= ADRENO_2XX_GEN2;  in adreno_is_a2xx()
301 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a20x()
303 	return gpu->info->family == ADRENO_2XX_GEN1;  in adreno_is_a20x()
318 	return gpu->info->chip_ids[0] == 0x03000512;  in adreno_is_a305b()
340 	return adreno_is_revn(gpu, 330);  in adreno_is_a330()
425 	return gpu->info->chip_ids[0] == 0x06020100;  in adreno_is_a621()
445 	return gpu->info->chip_ids[0] == 0x06030500;  in adreno_is_7c3()
460 	return gpu->info->chip_ids[0] == 0x06090000;  in adreno_is_a690()
465 	return gpu->info->chip_ids[0] == 0x07000200;  in adreno_is_a702()
470 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a610_family()
486 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a630_family()
488 	return gpu->info->family == ADRENO_6XX_GEN1;  in adreno_is_a630_family()
493 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a660_family()
495 	return gpu->info->family == ADRENO_6XX_GEN4;  in adreno_is_a660_family()
501 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a650_family()
503 	return gpu->info->family == ADRENO_6XX_GEN3 ||  in adreno_is_a650_family()
504 	       gpu->info->family == ADRENO_6XX_GEN4;  in adreno_is_a650_family()
509 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a640_family()
511 	return gpu->info->family == ADRENO_6XX_GEN2;  in adreno_is_a640_family()
516 	return gpu->info->chip_ids[0] == 0x07030001;  in adreno_is_a730()
521 	return gpu->info->chip_ids[0] == 0x43050a01;  in adreno_is_a740()
526 	return gpu->info->chip_ids[0] == 0x43051401;  in adreno_is_a750()
531 	return gpu->info->chip_ids[0] == 0x43050c01;  in adreno_is_x185()
536 	if (WARN_ON_ONCE(!gpu->info))  in adreno_is_a740_family()
538 	return gpu->info->family == ADRENO_7XX_GEN2 ||  in adreno_is_a740_family()
539 	       gpu->info->family == ADRENO_7XX_GEN3;  in adreno_is_a740_family()
544 	/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */  in adreno_is_a7xx()
545 	return gpu->info->family == ADRENO_7XX_GEN1 ||  in adreno_is_a7xx()
589  * Common helper function to initialize the default address space for arm-smmu
613 /* ringbuffer helpers (the parts that are adreno specific) */
619 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));  in OUT_PKT0()
622 /* no-op packet: */
634 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));  in OUT_PKT3()
675 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);  in get_wptr()
680  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
686  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
704 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \