Lines Matching +full:fixed +full:- +full:header
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
8 #include <soc/qcom/cmd-db.h>
31 struct a6xx_hfi_queue_header *header = queue->header; in a6xx_hfi_queue_read() local
32 u32 i, hdr, index = header->read_index; in a6xx_hfi_queue_read()
34 if (header->read_index == header->write_index) { in a6xx_hfi_queue_read()
35 header->rx_request = 1; in a6xx_hfi_queue_read()
39 hdr = queue->data[index]; in a6xx_hfi_queue_read()
41 queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index; in a6xx_hfi_queue_read()
46 * then we can also assume that if the header size is unexpectedly large in a6xx_hfi_queue_read()
55 data[i] = queue->data[index]; in a6xx_hfi_queue_read()
56 index = (index + 1) % header->size; in a6xx_hfi_queue_read()
59 if (!gmu->legacy) in a6xx_hfi_queue_read()
60 index = ALIGN(index, 4) % header->size; in a6xx_hfi_queue_read()
62 header->read_index = index; in a6xx_hfi_queue_read()
69 struct a6xx_hfi_queue_header *header = queue->header; in a6xx_hfi_queue_write() local
70 u32 i, space, index = header->write_index; in a6xx_hfi_queue_write()
72 spin_lock(&queue->lock); in a6xx_hfi_queue_write()
74 space = CIRC_SPACE(header->write_index, header->read_index, in a6xx_hfi_queue_write()
75 header->size); in a6xx_hfi_queue_write()
77 header->dropped++; in a6xx_hfi_queue_write()
78 spin_unlock(&queue->lock); in a6xx_hfi_queue_write()
79 return -ENOSPC; in a6xx_hfi_queue_write()
82 queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index; in a6xx_hfi_queue_write()
85 queue->data[index] = data[i]; in a6xx_hfi_queue_write()
86 index = (index + 1) % header->size; in a6xx_hfi_queue_write()
90 if (!gmu->legacy) { in a6xx_hfi_queue_write()
91 for (; index % 4; index = (index + 1) % header->size) in a6xx_hfi_queue_write()
92 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
95 header->write_index = index; in a6xx_hfi_queue_write()
96 spin_unlock(&queue->lock); in a6xx_hfi_queue_write()
105 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
114 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
117 return -ETIMEDOUT; in a6xx_hfi_wait_for_ack()
133 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
136 return -ENOENT; in a6xx_hfi_wait_for_ack()
139 if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) { in a6xx_hfi_wait_for_ack()
143 DRM_DEV_ERROR(gmu->dev, "GMU firmware error %d\n", in a6xx_hfi_wait_for_ack()
144 error->code); in a6xx_hfi_wait_for_ack()
149 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
156 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
159 return -EINVAL; in a6xx_hfi_wait_for_ack()
174 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_COMMAND_QUEUE]; in a6xx_hfi_send_msg()
178 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
180 /* First dword of the message is the message header - fill it in */ in a6xx_hfi_send_msg()
186 DRM_DEV_ERROR(gmu->dev, "Unable to send message %s id %d\n", in a6xx_hfi_send_msg()
198 msg.dbg_buffer_addr = (u32) gmu->debug.iova; in a6xx_hfi_send_gmu_init()
199 msg.dbg_buffer_size = (u32) gmu->debug.size; in a6xx_hfi_send_gmu_init()
222 msg.num_gpu_levels = gmu->nr_gpu_freqs; in a6xx_hfi_send_perf_table_v1()
223 msg.num_gmu_levels = gmu->nr_gmu_freqs; in a6xx_hfi_send_perf_table_v1()
225 for (i = 0; i < gmu->nr_gpu_freqs; i++) { in a6xx_hfi_send_perf_table_v1()
226 msg.gx_votes[i].vote = gmu->gx_arc_votes[i]; in a6xx_hfi_send_perf_table_v1()
227 msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000; in a6xx_hfi_send_perf_table_v1()
230 for (i = 0; i < gmu->nr_gmu_freqs; i++) { in a6xx_hfi_send_perf_table_v1()
231 msg.cx_votes[i].vote = gmu->cx_arc_votes[i]; in a6xx_hfi_send_perf_table_v1()
232 msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000; in a6xx_hfi_send_perf_table_v1()
244 msg.num_gpu_levels = gmu->nr_gpu_freqs; in a6xx_hfi_send_perf_table()
245 msg.num_gmu_levels = gmu->nr_gmu_freqs; in a6xx_hfi_send_perf_table()
247 for (i = 0; i < gmu->nr_gpu_freqs; i++) { in a6xx_hfi_send_perf_table()
248 msg.gx_votes[i].vote = gmu->gx_arc_votes[i]; in a6xx_hfi_send_perf_table()
250 msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000; in a6xx_hfi_send_perf_table()
253 for (i = 0; i < gmu->nr_gmu_freqs; i++) { in a6xx_hfi_send_perf_table()
254 msg.cx_votes[i].vote = gmu->cx_arc_votes[i]; in a6xx_hfi_send_perf_table()
255 msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000; in a6xx_hfi_send_perf_table()
265 msg->bw_level_num = 1; in a618_build_bw_table()
267 msg->ddr_cmds_num = 3; in a618_build_bw_table()
268 msg->ddr_wait_bitmask = 0x01; in a618_build_bw_table()
270 msg->ddr_cmds_addrs[0] = 0x50000; in a618_build_bw_table()
271 msg->ddr_cmds_addrs[1] = 0x5003c; in a618_build_bw_table()
272 msg->ddr_cmds_addrs[2] = 0x5000c; in a618_build_bw_table()
274 msg->ddr_cmds_data[0][0] = 0x40000000; in a618_build_bw_table()
275 msg->ddr_cmds_data[0][1] = 0x40000000; in a618_build_bw_table()
276 msg->ddr_cmds_data[0][2] = 0x40000000; in a618_build_bw_table()
279 * These are the CX (CNOC) votes - these are used by the GMU but the in a618_build_bw_table()
280 * votes are known and fixed for the target in a618_build_bw_table()
282 msg->cnoc_cmds_num = 1; in a618_build_bw_table()
283 msg->cnoc_wait_bitmask = 0x01; in a618_build_bw_table()
285 msg->cnoc_cmds_addrs[0] = 0x5007c; in a618_build_bw_table()
286 msg->cnoc_cmds_data[0][0] = 0x40000000; in a618_build_bw_table()
287 msg->cnoc_cmds_data[1][0] = 0x60000001; in a618_build_bw_table()
292 msg->bw_level_num = 13; in a619_build_bw_table()
294 msg->ddr_cmds_num = 3; in a619_build_bw_table()
295 msg->ddr_wait_bitmask = 0x0; in a619_build_bw_table()
297 msg->ddr_cmds_addrs[0] = 0x50000; in a619_build_bw_table()
298 msg->ddr_cmds_addrs[1] = 0x50004; in a619_build_bw_table()
299 msg->ddr_cmds_addrs[2] = 0x50080; in a619_build_bw_table()
301 msg->ddr_cmds_data[0][0] = 0x40000000; in a619_build_bw_table()
302 msg->ddr_cmds_data[0][1] = 0x40000000; in a619_build_bw_table()
303 msg->ddr_cmds_data[0][2] = 0x40000000; in a619_build_bw_table()
304 msg->ddr_cmds_data[1][0] = 0x6000030c; in a619_build_bw_table()
305 msg->ddr_cmds_data[1][1] = 0x600000db; in a619_build_bw_table()
306 msg->ddr_cmds_data[1][2] = 0x60000008; in a619_build_bw_table()
307 msg->ddr_cmds_data[2][0] = 0x60000618; in a619_build_bw_table()
308 msg->ddr_cmds_data[2][1] = 0x600001b6; in a619_build_bw_table()
309 msg->ddr_cmds_data[2][2] = 0x60000008; in a619_build_bw_table()
310 msg->ddr_cmds_data[3][0] = 0x60000925; in a619_build_bw_table()
311 msg->ddr_cmds_data[3][1] = 0x60000291; in a619_build_bw_table()
312 msg->ddr_cmds_data[3][2] = 0x60000008; in a619_build_bw_table()
313 msg->ddr_cmds_data[4][0] = 0x60000dc1; in a619_build_bw_table()
314 msg->ddr_cmds_data[4][1] = 0x600003dc; in a619_build_bw_table()
315 msg->ddr_cmds_data[4][2] = 0x60000008; in a619_build_bw_table()
316 msg->ddr_cmds_data[5][0] = 0x600010ad; in a619_build_bw_table()
317 msg->ddr_cmds_data[5][1] = 0x600004ae; in a619_build_bw_table()
318 msg->ddr_cmds_data[5][2] = 0x60000008; in a619_build_bw_table()
319 msg->ddr_cmds_data[6][0] = 0x600014c3; in a619_build_bw_table()
320 msg->ddr_cmds_data[6][1] = 0x600005d4; in a619_build_bw_table()
321 msg->ddr_cmds_data[6][2] = 0x60000008; in a619_build_bw_table()
322 msg->ddr_cmds_data[7][0] = 0x6000176a; in a619_build_bw_table()
323 msg->ddr_cmds_data[7][1] = 0x60000693; in a619_build_bw_table()
324 msg->ddr_cmds_data[7][2] = 0x60000008; in a619_build_bw_table()
325 msg->ddr_cmds_data[8][0] = 0x60001f01; in a619_build_bw_table()
326 msg->ddr_cmds_data[8][1] = 0x600008b5; in a619_build_bw_table()
327 msg->ddr_cmds_data[8][2] = 0x60000008; in a619_build_bw_table()
328 msg->ddr_cmds_data[9][0] = 0x60002940; in a619_build_bw_table()
329 msg->ddr_cmds_data[9][1] = 0x60000b95; in a619_build_bw_table()
330 msg->ddr_cmds_data[9][2] = 0x60000008; in a619_build_bw_table()
331 msg->ddr_cmds_data[10][0] = 0x60002f68; in a619_build_bw_table()
332 msg->ddr_cmds_data[10][1] = 0x60000d50; in a619_build_bw_table()
333 msg->ddr_cmds_data[10][2] = 0x60000008; in a619_build_bw_table()
334 msg->ddr_cmds_data[11][0] = 0x60003700; in a619_build_bw_table()
335 msg->ddr_cmds_data[11][1] = 0x60000f71; in a619_build_bw_table()
336 msg->ddr_cmds_data[11][2] = 0x60000008; in a619_build_bw_table()
337 msg->ddr_cmds_data[12][0] = 0x60003fce; in a619_build_bw_table()
338 msg->ddr_cmds_data[12][1] = 0x600011ea; in a619_build_bw_table()
339 msg->ddr_cmds_data[12][2] = 0x60000008; in a619_build_bw_table()
341 msg->cnoc_cmds_num = 1; in a619_build_bw_table()
342 msg->cnoc_wait_bitmask = 0x0; in a619_build_bw_table()
344 msg->cnoc_cmds_addrs[0] = 0x50054; in a619_build_bw_table()
346 msg->cnoc_cmds_data[0][0] = 0x40000000; in a619_build_bw_table()
355 msg->bw_level_num = 1; in a640_build_bw_table()
357 msg->ddr_cmds_num = 3; in a640_build_bw_table()
358 msg->ddr_wait_bitmask = 0x01; in a640_build_bw_table()
360 msg->ddr_cmds_addrs[0] = 0x50000; in a640_build_bw_table()
361 msg->ddr_cmds_addrs[1] = 0x5003c; in a640_build_bw_table()
362 msg->ddr_cmds_addrs[2] = 0x5000c; in a640_build_bw_table()
364 msg->ddr_cmds_data[0][0] = 0x40000000; in a640_build_bw_table()
365 msg->ddr_cmds_data[0][1] = 0x40000000; in a640_build_bw_table()
366 msg->ddr_cmds_data[0][2] = 0x40000000; in a640_build_bw_table()
369 * These are the CX (CNOC) votes - these are used by the GMU but the in a640_build_bw_table()
370 * votes are known and fixed for the target in a640_build_bw_table()
372 msg->cnoc_cmds_num = 3; in a640_build_bw_table()
373 msg->cnoc_wait_bitmask = 0x01; in a640_build_bw_table()
375 msg->cnoc_cmds_addrs[0] = 0x50034; in a640_build_bw_table()
376 msg->cnoc_cmds_addrs[1] = 0x5007c; in a640_build_bw_table()
377 msg->cnoc_cmds_addrs[2] = 0x5004c; in a640_build_bw_table()
379 msg->cnoc_cmds_data[0][0] = 0x40000000; in a640_build_bw_table()
380 msg->cnoc_cmds_data[0][1] = 0x00000000; in a640_build_bw_table()
381 msg->cnoc_cmds_data[0][2] = 0x40000000; in a640_build_bw_table()
383 msg->cnoc_cmds_data[1][0] = 0x60000001; in a640_build_bw_table()
384 msg->cnoc_cmds_data[1][1] = 0x20000001; in a640_build_bw_table()
385 msg->cnoc_cmds_data[1][2] = 0x60000001; in a640_build_bw_table()
394 msg->bw_level_num = 1; in a650_build_bw_table()
396 msg->ddr_cmds_num = 3; in a650_build_bw_table()
397 msg->ddr_wait_bitmask = 0x01; in a650_build_bw_table()
399 msg->ddr_cmds_addrs[0] = 0x50000; in a650_build_bw_table()
400 msg->ddr_cmds_addrs[1] = 0x50004; in a650_build_bw_table()
401 msg->ddr_cmds_addrs[2] = 0x5007c; in a650_build_bw_table()
403 msg->ddr_cmds_data[0][0] = 0x40000000; in a650_build_bw_table()
404 msg->ddr_cmds_data[0][1] = 0x40000000; in a650_build_bw_table()
405 msg->ddr_cmds_data[0][2] = 0x40000000; in a650_build_bw_table()
408 * These are the CX (CNOC) votes - these are used by the GMU but the in a650_build_bw_table()
409 * votes are known and fixed for the target in a650_build_bw_table()
411 msg->cnoc_cmds_num = 1; in a650_build_bw_table()
412 msg->cnoc_wait_bitmask = 0x01; in a650_build_bw_table()
414 msg->cnoc_cmds_addrs[0] = 0x500a4; in a650_build_bw_table()
415 msg->cnoc_cmds_data[0][0] = 0x40000000; in a650_build_bw_table()
416 msg->cnoc_cmds_data[1][0] = 0x60000001; in a650_build_bw_table()
425 msg->bw_level_num = 1; in a690_build_bw_table()
427 msg->ddr_cmds_num = 3; in a690_build_bw_table()
428 msg->ddr_wait_bitmask = 0x01; in a690_build_bw_table()
430 msg->ddr_cmds_addrs[0] = 0x50004; in a690_build_bw_table()
431 msg->ddr_cmds_addrs[1] = 0x50000; in a690_build_bw_table()
432 msg->ddr_cmds_addrs[2] = 0x500ac; in a690_build_bw_table()
434 msg->ddr_cmds_data[0][0] = 0x40000000; in a690_build_bw_table()
435 msg->ddr_cmds_data[0][1] = 0x40000000; in a690_build_bw_table()
436 msg->ddr_cmds_data[0][2] = 0x40000000; in a690_build_bw_table()
439 * These are the CX (CNOC) votes - these are used by the GMU but the in a690_build_bw_table()
440 * votes are known and fixed for the target in a690_build_bw_table()
442 msg->cnoc_cmds_num = 1; in a690_build_bw_table()
443 msg->cnoc_wait_bitmask = 0x01; in a690_build_bw_table()
445 msg->cnoc_cmds_addrs[0] = 0x5003c; in a690_build_bw_table()
446 msg->cnoc_cmds_data[0][0] = 0x40000000; in a690_build_bw_table()
447 msg->cnoc_cmds_data[1][0] = 0x60000001; in a690_build_bw_table()
456 msg->bw_level_num = 1; in a660_build_bw_table()
458 msg->ddr_cmds_num = 3; in a660_build_bw_table()
459 msg->ddr_wait_bitmask = 0x01; in a660_build_bw_table()
461 msg->ddr_cmds_addrs[0] = 0x50004; in a660_build_bw_table()
462 msg->ddr_cmds_addrs[1] = 0x500a0; in a660_build_bw_table()
463 msg->ddr_cmds_addrs[2] = 0x50000; in a660_build_bw_table()
465 msg->ddr_cmds_data[0][0] = 0x40000000; in a660_build_bw_table()
466 msg->ddr_cmds_data[0][1] = 0x40000000; in a660_build_bw_table()
467 msg->ddr_cmds_data[0][2] = 0x40000000; in a660_build_bw_table()
470 * These are the CX (CNOC) votes - these are used by the GMU but the in a660_build_bw_table()
471 * votes are known and fixed for the target in a660_build_bw_table()
473 msg->cnoc_cmds_num = 1; in a660_build_bw_table()
474 msg->cnoc_wait_bitmask = 0x01; in a660_build_bw_table()
476 msg->cnoc_cmds_addrs[0] = 0x50070; in a660_build_bw_table()
477 msg->cnoc_cmds_data[0][0] = 0x40000000; in a660_build_bw_table()
478 msg->cnoc_cmds_data[1][0] = 0x60000001; in a660_build_bw_table()
487 msg->bw_level_num = 1; in adreno_7c3_build_bw_table()
489 msg->ddr_cmds_num = 3; in adreno_7c3_build_bw_table()
490 msg->ddr_wait_bitmask = 0x07; in adreno_7c3_build_bw_table()
492 msg->ddr_cmds_addrs[0] = 0x50004; in adreno_7c3_build_bw_table()
493 msg->ddr_cmds_addrs[1] = 0x50000; in adreno_7c3_build_bw_table()
494 msg->ddr_cmds_addrs[2] = 0x50088; in adreno_7c3_build_bw_table()
496 msg->ddr_cmds_data[0][0] = 0x40000000; in adreno_7c3_build_bw_table()
497 msg->ddr_cmds_data[0][1] = 0x40000000; in adreno_7c3_build_bw_table()
498 msg->ddr_cmds_data[0][2] = 0x40000000; in adreno_7c3_build_bw_table()
501 * These are the CX (CNOC) votes - these are used by the GMU but the in adreno_7c3_build_bw_table()
502 * votes are known and fixed for the target in adreno_7c3_build_bw_table()
504 msg->cnoc_cmds_num = 1; in adreno_7c3_build_bw_table()
505 msg->cnoc_wait_bitmask = 0x01; in adreno_7c3_build_bw_table()
507 msg->cnoc_cmds_addrs[0] = 0x5006c; in adreno_7c3_build_bw_table()
508 msg->cnoc_cmds_data[0][0] = 0x40000000; in adreno_7c3_build_bw_table()
509 msg->cnoc_cmds_data[1][0] = 0x60000001; in adreno_7c3_build_bw_table()
514 msg->bw_level_num = 12; in a730_build_bw_table()
516 msg->ddr_cmds_num = 3; in a730_build_bw_table()
517 msg->ddr_wait_bitmask = 0x7; in a730_build_bw_table()
519 msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0"); in a730_build_bw_table()
520 msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0"); in a730_build_bw_table()
521 msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV"); in a730_build_bw_table()
523 msg->ddr_cmds_data[0][0] = 0x40000000; in a730_build_bw_table()
524 msg->ddr_cmds_data[0][1] = 0x40000000; in a730_build_bw_table()
525 msg->ddr_cmds_data[0][2] = 0x40000000; in a730_build_bw_table()
526 msg->ddr_cmds_data[1][0] = 0x600002e8; in a730_build_bw_table()
527 msg->ddr_cmds_data[1][1] = 0x600003d0; in a730_build_bw_table()
528 msg->ddr_cmds_data[1][2] = 0x60000008; in a730_build_bw_table()
529 msg->ddr_cmds_data[2][0] = 0x6000068d; in a730_build_bw_table()
530 msg->ddr_cmds_data[2][1] = 0x6000089a; in a730_build_bw_table()
531 msg->ddr_cmds_data[2][2] = 0x60000008; in a730_build_bw_table()
532 msg->ddr_cmds_data[3][0] = 0x600007f2; in a730_build_bw_table()
533 msg->ddr_cmds_data[3][1] = 0x60000a6e; in a730_build_bw_table()
534 msg->ddr_cmds_data[3][2] = 0x60000008; in a730_build_bw_table()
535 msg->ddr_cmds_data[4][0] = 0x600009e5; in a730_build_bw_table()
536 msg->ddr_cmds_data[4][1] = 0x60000cfd; in a730_build_bw_table()
537 msg->ddr_cmds_data[4][2] = 0x60000008; in a730_build_bw_table()
538 msg->ddr_cmds_data[5][0] = 0x60000b29; in a730_build_bw_table()
539 msg->ddr_cmds_data[5][1] = 0x60000ea6; in a730_build_bw_table()
540 msg->ddr_cmds_data[5][2] = 0x60000008; in a730_build_bw_table()
541 msg->ddr_cmds_data[6][0] = 0x60001698; in a730_build_bw_table()
542 msg->ddr_cmds_data[6][1] = 0x60001da8; in a730_build_bw_table()
543 msg->ddr_cmds_data[6][2] = 0x60000008; in a730_build_bw_table()
544 msg->ddr_cmds_data[7][0] = 0x600018d2; in a730_build_bw_table()
545 msg->ddr_cmds_data[7][1] = 0x60002093; in a730_build_bw_table()
546 msg->ddr_cmds_data[7][2] = 0x60000008; in a730_build_bw_table()
547 msg->ddr_cmds_data[8][0] = 0x60001e66; in a730_build_bw_table()
548 msg->ddr_cmds_data[8][1] = 0x600027e6; in a730_build_bw_table()
549 msg->ddr_cmds_data[8][2] = 0x60000008; in a730_build_bw_table()
550 msg->ddr_cmds_data[9][0] = 0x600027c2; in a730_build_bw_table()
551 msg->ddr_cmds_data[9][1] = 0x6000342f; in a730_build_bw_table()
552 msg->ddr_cmds_data[9][2] = 0x60000008; in a730_build_bw_table()
553 msg->ddr_cmds_data[10][0] = 0x60002e71; in a730_build_bw_table()
554 msg->ddr_cmds_data[10][1] = 0x60003cf5; in a730_build_bw_table()
555 msg->ddr_cmds_data[10][2] = 0x60000008; in a730_build_bw_table()
556 msg->ddr_cmds_data[11][0] = 0x600030ae; in a730_build_bw_table()
557 msg->ddr_cmds_data[11][1] = 0x60003fe5; in a730_build_bw_table()
558 msg->ddr_cmds_data[11][2] = 0x60000008; in a730_build_bw_table()
560 msg->cnoc_cmds_num = 1; in a730_build_bw_table()
561 msg->cnoc_wait_bitmask = 0x1; in a730_build_bw_table()
563 msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); in a730_build_bw_table()
564 msg->cnoc_cmds_data[0][0] = 0x40000000; in a730_build_bw_table()
565 msg->cnoc_cmds_data[1][0] = 0x60000001; in a730_build_bw_table()
570 msg->bw_level_num = 1; in a740_build_bw_table()
572 msg->ddr_cmds_num = 3; in a740_build_bw_table()
573 msg->ddr_wait_bitmask = 0x7; in a740_build_bw_table()
575 msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0"); in a740_build_bw_table()
576 msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0"); in a740_build_bw_table()
577 msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV"); in a740_build_bw_table()
579 msg->ddr_cmds_data[0][0] = 0x40000000; in a740_build_bw_table()
580 msg->ddr_cmds_data[0][1] = 0x40000000; in a740_build_bw_table()
581 msg->ddr_cmds_data[0][2] = 0x40000000; in a740_build_bw_table()
585 msg->cnoc_cmds_num = 1; in a740_build_bw_table()
586 msg->cnoc_wait_bitmask = 0x1; in a740_build_bw_table()
588 msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); in a740_build_bw_table()
589 msg->cnoc_cmds_data[0][0] = 0x40000000; in a740_build_bw_table()
590 msg->cnoc_cmds_data[1][0] = 0x60000001; in a740_build_bw_table()
596 msg->bw_level_num = 1; in a6xx_build_bw_table()
598 msg->ddr_cmds_num = 3; in a6xx_build_bw_table()
599 msg->ddr_wait_bitmask = 0x07; in a6xx_build_bw_table()
601 msg->ddr_cmds_addrs[0] = 0x50000; in a6xx_build_bw_table()
602 msg->ddr_cmds_addrs[1] = 0x5005c; in a6xx_build_bw_table()
603 msg->ddr_cmds_addrs[2] = 0x5000c; in a6xx_build_bw_table()
605 msg->ddr_cmds_data[0][0] = 0x40000000; in a6xx_build_bw_table()
606 msg->ddr_cmds_data[0][1] = 0x40000000; in a6xx_build_bw_table()
607 msg->ddr_cmds_data[0][2] = 0x40000000; in a6xx_build_bw_table()
611 * sdm845 GMU are known and fixed so we can hard code them. in a6xx_build_bw_table()
614 msg->cnoc_cmds_num = 3; in a6xx_build_bw_table()
615 msg->cnoc_wait_bitmask = 0x05; in a6xx_build_bw_table()
617 msg->cnoc_cmds_addrs[0] = 0x50034; in a6xx_build_bw_table()
618 msg->cnoc_cmds_addrs[1] = 0x5007c; in a6xx_build_bw_table()
619 msg->cnoc_cmds_addrs[2] = 0x5004c; in a6xx_build_bw_table()
621 msg->cnoc_cmds_data[0][0] = 0x40000000; in a6xx_build_bw_table()
622 msg->cnoc_cmds_data[0][1] = 0x00000000; in a6xx_build_bw_table()
623 msg->cnoc_cmds_data[0][2] = 0x40000000; in a6xx_build_bw_table()
625 msg->cnoc_cmds_data[1][0] = 0x60000001; in a6xx_build_bw_table()
626 msg->cnoc_cmds_data[1][1] = 0x20000001; in a6xx_build_bw_table()
627 msg->cnoc_cmds_data[1][2] = 0x60000001; in a6xx_build_bw_table()
635 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_hfi_send_bw_table()
702 /* TODO: should freq and bw fields be non-zero ? */ in a6xx_hfi_send_prep_slumber()
747 if (gmu->legacy) in a6xx_hfi_start()
778 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_hfi_stop()
779 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_hfi_stop()
781 if (!queue->header) in a6xx_hfi_stop()
784 if (queue->header->read_index != queue->header->write_index) in a6xx_hfi_stop()
785 DRM_DEV_ERROR(gmu->dev, "HFI queue %d is not empty\n", i); in a6xx_hfi_stop()
787 queue->header->read_index = 0; in a6xx_hfi_stop()
788 queue->header->write_index = 0; in a6xx_hfi_stop()
790 memset(&queue->history, 0xff, sizeof(queue->history)); in a6xx_hfi_stop()
791 queue->history_idx = 0; in a6xx_hfi_stop()
796 struct a6xx_hfi_queue_header *header, void *virt, u64 iova, in a6xx_hfi_queue_init() argument
799 spin_lock_init(&queue->lock); in a6xx_hfi_queue_init()
800 queue->header = header; in a6xx_hfi_queue_init()
801 queue->data = virt; in a6xx_hfi_queue_init()
802 atomic_set(&queue->seqnum, 0); in a6xx_hfi_queue_init()
804 memset(&queue->history, 0xff, sizeof(queue->history)); in a6xx_hfi_queue_init()
805 queue->history_idx = 0; in a6xx_hfi_queue_init()
807 /* Set up the shared memory header */ in a6xx_hfi_queue_init()
808 header->iova = iova; in a6xx_hfi_queue_init()
809 header->type = 10 << 8 | id; in a6xx_hfi_queue_init()
810 header->status = 1; in a6xx_hfi_queue_init()
811 header->size = SZ_4K >> 2; in a6xx_hfi_queue_init()
812 header->msg_size = 0; in a6xx_hfi_queue_init()
813 header->dropped = 0; in a6xx_hfi_queue_init()
814 header->rx_watermark = 1; in a6xx_hfi_queue_init()
815 header->tx_watermark = 1; in a6xx_hfi_queue_init()
816 header->rx_request = 1; in a6xx_hfi_queue_init()
817 header->tx_request = 0; in a6xx_hfi_queue_init()
818 header->read_index = 0; in a6xx_hfi_queue_init()
819 header->write_index = 0; in a6xx_hfi_queue_init()
824 struct a6xx_gmu_bo *hfi = &gmu->hfi; in a6xx_hfi_init()
825 struct a6xx_hfi_queue_table_header *table = hfi->virt; in a6xx_hfi_init()
826 struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table); in a6xx_hfi_init()
831 * The table size is the size of the table header plus all of the queue in a6xx_hfi_init()
835 table_size += (ARRAY_SIZE(gmu->queues) * in a6xx_hfi_init()
838 table->version = 0; in a6xx_hfi_init()
839 table->size = table_size; in a6xx_hfi_init()
840 /* First queue header is located immediately after the table header */ in a6xx_hfi_init()
841 table->qhdr0_offset = sizeof(*table) >> 2; in a6xx_hfi_init()
842 table->qhdr_size = sizeof(struct a6xx_hfi_queue_header) >> 2; in a6xx_hfi_init()
843 table->num_queues = ARRAY_SIZE(gmu->queues); in a6xx_hfi_init()
844 table->active_queues = ARRAY_SIZE(gmu->queues); in a6xx_hfi_init()
848 a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset, in a6xx_hfi_init()
849 hfi->iova + offset, 0); in a6xx_hfi_init()
853 a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset, in a6xx_hfi_init()
854 hfi->iova + offset, gmu->legacy ? 4 : 1); in a6xx_hfi_init()