Lines Matching +full:adreno +full:- +full:gmu +full:- +full:wrapper
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
24 /* Check that the GMU is idle */ in _a6xx_check_idle()
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
45 gpu->name, __builtin_return_address(0), in a6xx_idle()
62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { in update_shadow_rptr()
76 spin_lock_irqsave(&ring->preempt_lock, flags); in a6xx_flush()
79 ring->cur = ring->next; in a6xx_flush()
84 spin_unlock_irqrestore(&ring->preempt_lock, flags); in a6xx_flush()
106 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; in a6xx_set_pagetable()
107 struct msm_file_private *ctx = submit->queue->ctx; in a6xx_set_pagetable()
108 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_set_pagetable()
113 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno) in a6xx_set_pagetable()
116 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
119 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { in a6xx_set_pagetable()
125 OUT_RING(ring, submit->seqno - 1); in a6xx_set_pagetable()
163 if (adreno_is_a7xx(&a6xx_gpu->base)) { in a6xx_set_pagetable()
191 /* Re-enable protected mode: */ in a6xx_set_pagetable()
200 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; in a6xx_submit()
203 struct msm_ringbuffer *ring = submit->ring; in a6xx_submit()
212 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
227 for (i = 0; i < submit->nr_cmds; i++) { in a6xx_submit()
228 switch (submit->cmd[i].type) { in a6xx_submit()
232 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a6xx_submit()
237 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a6xx_submit()
238 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); in a6xx_submit()
239 OUT_RING(ring, submit->cmd[i].size); in a6xx_submit()
245 * Periodically update shadow-wptr if needed, so that we in a6xx_submit()
262 OUT_RING(ring, submit->seqno); in a6xx_submit()
273 OUT_RING(ring, submit->seqno); in a6xx_submit()
283 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; in a7xx_submit()
286 struct msm_ringbuffer *ring = submit->ring; in a7xx_submit()
313 for (i = 0; i < submit->nr_cmds; i++) { in a7xx_submit()
314 switch (submit->cmd[i].type) { in a7xx_submit()
318 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a7xx_submit()
323 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a7xx_submit()
324 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); in a7xx_submit()
325 OUT_RING(ring, submit->cmd[i].size); in a7xx_submit()
331 * Periodically update shadow-wptr if needed, so that we in a7xx_submit()
351 OUT_RING(ring, submit->seqno); in a7xx_submit()
373 OUT_RING(ring, submit->seqno); in a7xx_submit()
387 OUT_RING(ring, submit->seqno); in a7xx_submit()
394 OUT_RING(ring, submit->seqno); in a7xx_submit()
412 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
418 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) in a6xx_set_hwcg()
433 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
434 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); in a6xx_set_hwcg()
435 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
437 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
440 if (!adreno_gpu->info->a6xx->hwcg) { in a6xx_set_hwcg()
449 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); in a6xx_set_hwcg()
461 /* Don't re-program the registers if they are already correct */ in a6xx_set_hwcg()
467 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
469 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) in a6xx_set_hwcg()
470 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
474 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
482 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; in a6xx_set_cp_protect()
495 for (i = 0; i < protect->count - 1; i++) { in a6xx_set_cp_protect()
497 if (protect->regs[i]) in a6xx_set_cp_protect()
498 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); in a6xx_set_cp_protect()
501 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); in a6xx_set_cp_protect()
506 gpu->ubwc_config.rgb565_predicator = 0; in a6xx_calc_ubwc_config()
507 gpu->ubwc_config.uavflagprd_inv = 0; in a6xx_calc_ubwc_config()
508 gpu->ubwc_config.min_acc_len = 0; in a6xx_calc_ubwc_config()
509 gpu->ubwc_config.ubwc_swizzle = 0x6; in a6xx_calc_ubwc_config()
510 gpu->ubwc_config.macrotile_mode = 0; in a6xx_calc_ubwc_config()
511 gpu->ubwc_config.highest_bank_bit = 15; in a6xx_calc_ubwc_config()
514 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
515 gpu->ubwc_config.min_acc_len = 1; in a6xx_calc_ubwc_config()
516 gpu->ubwc_config.ubwc_swizzle = 0x7; in a6xx_calc_ubwc_config()
520 gpu->ubwc_config.highest_bank_bit = 14; in a6xx_calc_ubwc_config()
524 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
527 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
530 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
531 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
532 gpu->ubwc_config.uavflagprd_inv = 2; in a6xx_calc_ubwc_config()
536 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
539 gpu->ubwc_config.macrotile_mode = 1; in a6xx_calc_ubwc_config()
547 gpu->ubwc_config.highest_bank_bit = 16; in a6xx_calc_ubwc_config()
548 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
549 gpu->ubwc_config.rgb565_predicator = 1; in a6xx_calc_ubwc_config()
550 gpu->ubwc_config.uavflagprd_inv = 2; in a6xx_calc_ubwc_config()
551 gpu->ubwc_config.macrotile_mode = 1; in a6xx_calc_ubwc_config()
555 gpu->ubwc_config.highest_bank_bit = 14; in a6xx_calc_ubwc_config()
556 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
557 gpu->ubwc_config.rgb565_predicator = 1; in a6xx_calc_ubwc_config()
558 gpu->ubwc_config.uavflagprd_inv = 2; in a6xx_calc_ubwc_config()
559 gpu->ubwc_config.macrotile_mode = 1; in a6xx_calc_ubwc_config()
563 gpu->ubwc_config.highest_bank_bit = 14; in a6xx_calc_ubwc_config()
564 gpu->ubwc_config.min_acc_len = 1; in a6xx_calc_ubwc_config()
576 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); in a6xx_set_ubwc_config()
577 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; in a6xx_set_ubwc_config()
580 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; in a6xx_set_ubwc_config()
581 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); in a6xx_set_ubwc_config()
585 adreno_gpu->ubwc_config.rgb565_predicator << 11 | in a6xx_set_ubwc_config()
586 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | in a6xx_set_ubwc_config()
587 adreno_gpu->ubwc_config.min_acc_len << 3 | in a6xx_set_ubwc_config()
592 adreno_gpu->ubwc_config.min_acc_len << 3 | in a6xx_set_ubwc_config()
597 adreno_gpu->ubwc_config.uavflagprd_inv << 4 | in a6xx_set_ubwc_config()
598 adreno_gpu->ubwc_config.min_acc_len << 3 | in a6xx_set_ubwc_config()
606 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); in a6xx_set_ubwc_config()
609 adreno_gpu->ubwc_config.macrotile_mode); in a6xx_set_ubwc_config()
614 struct msm_ringbuffer *ring = gpu->rb[0]; in a6xx_cp_init()
638 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a6xx_cp_init()
643 struct msm_ringbuffer *ring = gpu->rb[0]; in a7xx_cp_init()
687 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a7xx_cp_init()
697 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_ucode_check_version()
698 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_ucode_check_version()
699 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; in a6xx_ucode_check_version()
733 a6xx_gpu->has_whereami = true; in a6xx_ucode_check_version()
738 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
747 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
753 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
766 if (!a6xx_gpu->sqe_bo) { in a6xx_ucode_load()
767 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, in a6xx_ucode_load()
768 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); in a6xx_ucode_load()
770 if (IS_ERR(a6xx_gpu->sqe_bo)) { in a6xx_ucode_load()
771 int ret = PTR_ERR(a6xx_gpu->sqe_bo); in a6xx_ucode_load()
773 a6xx_gpu->sqe_bo = NULL; in a6xx_ucode_load()
774 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_load()
780 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); in a6xx_ucode_load()
781 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { in a6xx_ucode_load()
782 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_ucode_load()
783 drm_gem_object_put(a6xx_gpu->sqe_bo); in a6xx_ucode_load()
785 a6xx_gpu->sqe_bo = NULL; in a6xx_ucode_load()
786 return -EPERM; in a6xx_ucode_load()
794 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && in a6xx_ucode_load()
795 !a6xx_gpu->shadow_bo) { in a6xx_ucode_load()
796 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, in a6xx_ucode_load()
797 sizeof(u32) * gpu->nr_rings, in a6xx_ucode_load()
799 gpu->aspace, &a6xx_gpu->shadow_bo, in a6xx_ucode_load()
800 &a6xx_gpu->shadow_iova); in a6xx_ucode_load()
802 if (IS_ERR(a6xx_gpu->shadow)) in a6xx_ucode_load()
803 return PTR_ERR(a6xx_gpu->shadow); in a6xx_ucode_load()
805 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); in a6xx_ucode_load()
865 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
870 /* Make sure the GMU keeps the GPU on while we set it up */ in hw_init()
871 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
894 a6xx_sptprac_enable(gmu); in hw_init()
897 * Disable the trusted memory range - we don't actually supported secure in hw_init()
962 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ in hw_init()
966 gmem_range_min + adreno_gpu->info->gmem - 1); in hw_init()
1002 if (adreno_gpu->info->a6xx->prim_fifo_threshold) in hw_init()
1004 adreno_gpu->info->a6xx->prim_fifo_threshold); in hw_init()
1014 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, in hw_init()
1051 /* Set up the CX GMU counter 0 to count busy ticks */ in hw_init()
1052 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in hw_init()
1055 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); in hw_init()
1056 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in hw_init()
1086 if (gpu->hw_apriv) { in hw_init()
1106 /* Disable non-ubwc read reqs from passing write reqs */ in hw_init()
1118 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); in hw_init()
1121 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1127 if (adreno_gpu->base.hw_apriv) in hw_init()
1134 if (a6xx_gpu->shadow_bo) { in hw_init()
1136 shadowptr(a6xx_gpu, gpu->rb[0])); in hw_init()
1142 rbmemptr(gpu->rb[0], bv_fence)); in hw_init()
1146 a6xx_gpu->cur_ring = gpu->rb[0]; in hw_init()
1148 gpu->cur_ctx_seqno = 0; in hw_init()
1166 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in hw_init()
1167 OUT_RING(gpu->rb[0], 0x00000000); in hw_init()
1169 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1170 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1171 return -EINVAL; in hw_init()
1172 } else if (ret == -ENODEV) { in hw_init()
1179 dev_warn_once(gpu->dev->dev, in hw_init()
1180 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); in hw_init()
1191 * Tell the GMU that we are done touching the GPU and it can start power in hw_init()
1194 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1196 if (a6xx_gpu->gmu.legacy) { in hw_init()
1197 /* Take the GMU out of its special boot mode */ in hw_init()
1198 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); in hw_init()
1210 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
1212 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
1219 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", in a6xx_dump()
1228 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_recover() local
1234 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, in a6xx_recover()
1244 a6xx_gpu->hung = true; in a6xx_recover()
1249 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
1252 mutex_lock(&gpu->active_lock); in a6xx_recover()
1253 active_submits = gpu->active_submits; in a6xx_recover()
1259 gpu->active_submits = 0; in a6xx_recover()
1270 reinit_completion(&gmu->pd_gate); in a6xx_recover()
1271 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); in a6xx_recover()
1272 dev_pm_genpd_synced_poweroff(gmu->cxpd); in a6xx_recover()
1276 pm_runtime_put(&gpu->pdev->dev); in a6xx_recover()
1279 pm_runtime_put_sync(&gpu->pdev->dev); in a6xx_recover()
1281 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) in a6xx_recover()
1282 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); in a6xx_recover()
1284 dev_pm_genpd_remove_notifier(gmu->cxpd); in a6xx_recover()
1286 pm_runtime_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
1289 pm_runtime_get(&gpu->pdev->dev); in a6xx_recover()
1291 pm_runtime_get_sync(&gpu->pdev->dev); in a6xx_recover()
1293 gpu->active_submits = active_submits; in a6xx_recover()
1294 mutex_unlock(&gpu->active_lock); in a6xx_recover()
1297 a6xx_gpu->hung = false; in a6xx_recover()
1332 * compute-only some of them do not exist and there are holes in a6xx_uche_fault_block()
1336 "-", "LPAC_SP", "-", "-", in a6xx_uche_fault_block()
1337 "LPAC_HLSQ", "-", "-", "LPAC_TP", in a6xx_uche_fault_block()
1408 return "GMU"; in a6xx_fault_block()
1429 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); in a6xx_fault_handler()
1443 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1449 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1453 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", in a6xx_cp_hw_err_irq()
1459 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1466 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); in a6xx_cp_hw_err_irq()
1469 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); in a6xx_cp_hw_err_irq()
1472 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); in a6xx_cp_hw_err_irq()
1480 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a6xx_fault_detect_irq()
1496 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); in a6xx_fault_detect_irq()
1498 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_fault_detect_irq()
1500 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, in a6xx_fault_detect_irq()
1510 del_timer(&gpu->hangcheck_timer); in a6xx_fault_detect_irq()
1512 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_fault_detect_irq()
1522 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); in a7xx_sw_fuse_violation_irq()
1530 del_timer(&gpu->hangcheck_timer); in a7xx_sw_fuse_violation_irq()
1532 kthread_queue_work(gpu->worker, &gpu->recover_work); in a7xx_sw_fuse_violation_irq()
1538 struct msm_drm_private *priv = gpu->dev->dev_private; in a6xx_irq()
1543 if (priv->disable_err_irq) in a6xx_irq()
1550 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); in a6xx_irq()
1556 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); in a6xx_irq()
1559 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); in a6xx_irq()
1562 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); in a6xx_irq()
1575 llcc_slice_deactivate(a6xx_gpu->llc_slice); in a6xx_llc_deactivate()
1576 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); in a6xx_llc_deactivate()
1581 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_llc_activate()
1582 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_llc_activate()
1585 if (IS_ERR(a6xx_gpu->llc_mmio)) in a6xx_llc_activate()
1588 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { in a6xx_llc_activate()
1589 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); in a6xx_llc_activate()
1607 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { in a6xx_llc_activate()
1608 if (!a6xx_gpu->have_mmu500) { in a6xx_llc_activate()
1609 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); in a6xx_llc_activate()
1623 if (!a6xx_gpu->have_mmu500) { in a6xx_llc_activate()
1641 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a7xx_llc_activate()
1642 struct msm_gpu *gpu = &adreno_gpu->base; in a7xx_llc_activate()
1644 if (IS_ERR(a6xx_gpu->llc_mmio)) in a7xx_llc_activate()
1647 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { in a7xx_llc_activate()
1648 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); in a7xx_llc_activate()
1665 llcc_slice_activate(a6xx_gpu->htw_llc_slice); in a7xx_llc_activate()
1670 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_destroy()
1671 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) in a6xx_llc_slices_destroy()
1674 llcc_slice_putd(a6xx_gpu->llc_slice); in a6xx_llc_slices_destroy()
1675 llcc_slice_putd(a6xx_gpu->htw_llc_slice); in a6xx_llc_slices_destroy()
1683 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_init()
1684 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) in a6xx_llc_slices_init()
1691 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); in a6xx_llc_slices_init()
1692 a6xx_gpu->have_mmu500 = (phandle && in a6xx_llc_slices_init()
1693 of_device_is_compatible(phandle, "arm,mmu-500")); in a6xx_llc_slices_init()
1696 if (is_a7xx || !a6xx_gpu->have_mmu500) in a6xx_llc_slices_init()
1697 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); in a6xx_llc_slices_init()
1699 a6xx_gpu->llc_mmio = NULL; in a6xx_llc_slices_init()
1701 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); in a6xx_llc_slices_init()
1702 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); in a6xx_llc_slices_init()
1704 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) in a6xx_llc_slices_init()
1705 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); in a6xx_llc_slices_init()
1710 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a7xx_cx_mem_init()
1711 struct msm_gpu *gpu = &adreno_gpu->base; in a7xx_cx_mem_init()
1725 dev_warn_once(gpu->dev->dev, in a7xx_cx_mem_init()
1731 adreno_gpu->has_ray_tracing = true; in a7xx_cx_mem_init()
1747 adreno_gpu->has_ray_tracing = in a7xx_cx_mem_init()
1751 adreno_gpu->has_ray_tracing = true; in a7xx_cx_mem_init()
1766 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_bus_clear_pending_transactions()
1823 gpu->needs_hw_init = true; in a6xx_gmu_pm_resume()
1827 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_resume()
1829 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_resume()
1844 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_pm_resume() local
1845 unsigned long freq = gpu->fast_rate; in a6xx_pm_resume()
1849 gpu->needs_hw_init = true; in a6xx_pm_resume()
1853 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_pm_resume()
1855 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); in a6xx_pm_resume()
1863 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); in a6xx_pm_resume()
1865 pm_runtime_resume_and_get(gmu->dev); in a6xx_pm_resume()
1866 pm_runtime_resume_and_get(gmu->gxpd); in a6xx_pm_resume()
1868 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_resume()
1873 a6xx_sptprac_enable(gmu); in a6xx_pm_resume()
1878 pm_runtime_put(gmu->gxpd); in a6xx_pm_resume()
1879 pm_runtime_put(gmu->dev); in a6xx_pm_resume()
1880 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); in a6xx_pm_resume()
1883 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_pm_resume()
1903 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_suspend()
1905 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_suspend()
1909 if (a6xx_gpu->shadow_bo) in a6xx_gmu_pm_suspend()
1910 for (i = 0; i < gpu->nr_rings; i++) in a6xx_gmu_pm_suspend()
1911 a6xx_gpu->shadow[i] = 0; in a6xx_gmu_pm_suspend()
1913 gpu->suspend_count++; in a6xx_gmu_pm_suspend()
1922 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_pm_suspend() local
1929 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_pm_suspend()
1935 a6xx_sptprac_disable(gmu); in a6xx_pm_suspend()
1937 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_suspend()
1939 pm_runtime_put_sync(gmu->gxpd); in a6xx_pm_suspend()
1940 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); in a6xx_pm_suspend()
1941 pm_runtime_put_sync(gmu->dev); in a6xx_pm_suspend()
1943 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_pm_suspend()
1945 if (a6xx_gpu->shadow_bo) in a6xx_pm_suspend()
1946 for (i = 0; i < gpu->nr_rings; i++) in a6xx_pm_suspend()
1947 a6xx_gpu->shadow[i] = 0; in a6xx_pm_suspend()
1949 gpu->suspend_count++; in a6xx_pm_suspend()
1959 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_get_timestamp()
1962 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); in a6xx_gmu_get_timestamp()
1966 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); in a6xx_gmu_get_timestamp()
1968 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_get_timestamp()
1984 return a6xx_gpu->cur_ring; in a6xx_active_ring()
1992 if (a6xx_gpu->sqe_bo) { in a6xx_destroy()
1993 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_destroy()
1994 drm_gem_object_put(a6xx_gpu->sqe_bo); in a6xx_destroy()
1997 if (a6xx_gpu->shadow_bo) { in a6xx_destroy()
1998 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); in a6xx_destroy()
1999 drm_gem_object_put(a6xx_gpu->shadow_bo); in a6xx_destroy()
2020 busy_cycles = gmu_read64(&a6xx_gpu->gmu, in a6xx_gpu_busy()
2033 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gpu_set_freq()
2035 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gpu_set_freq()
2049 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && in a6xx_create_address_space()
2050 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) in a6xx_create_address_space()
2061 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); in a6xx_create_private_address_space()
2076 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) in a6xx_get_rptr()
2077 return a6xx_gpu->shadow[ring->id]; in a6xx_get_rptr()
2079 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); in a6xx_get_rptr()
2108 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); in a6xx_progress()
2110 ring->last_cp_state = cp_state; in a6xx_progress()
2117 if (!info->speedbins) in fuse_to_supp_hw()
2120 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) in fuse_to_supp_hw()
2121 if (info->speedbins[i].fuse == fuse) in fuse_to_supp_hw()
2122 return BIT(info->speedbins[i].speedbin); in fuse_to_supp_hw()
2135 * -ENOENT means that the platform doesn't support speedbin which is in a6xx_set_supported_hw()
2138 if (ret == -ENOENT) { in a6xx_set_supported_hw()
2142 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); in a6xx_set_supported_hw()
2150 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", in a6xx_set_supported_hw()
2255 struct msm_drm_private *priv = dev->dev_private; in a6xx_gpu_init()
2256 struct platform_device *pdev = priv->gpu_pdev; in a6xx_gpu_init()
2257 struct adreno_platform_config *config = pdev->dev.platform_data; in a6xx_gpu_init()
2267 return ERR_PTR(-ENOMEM); in a6xx_gpu_init()
2269 adreno_gpu = &a6xx_gpu->base; in a6xx_gpu_init()
2270 gpu = &adreno_gpu->base; in a6xx_gpu_init()
2272 mutex_init(&a6xx_gpu->gmu.lock); in a6xx_gpu_init()
2274 adreno_gpu->registers = NULL; in a6xx_gpu_init()
2276 /* Check if there is a GMU phandle and set it up */ in a6xx_gpu_init()
2277 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); in a6xx_gpu_init()
2281 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); in a6xx_gpu_init()
2283 adreno_gpu->base.hw_apriv = in a6xx_gpu_init()
2284 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); in a6xx_gpu_init()
2286 /* gpu->info only gets assigned in adreno_gpu_init() */ in a6xx_gpu_init()
2287 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || in a6xx_gpu_init()
2288 config->info->family == ADRENO_7XX_GEN2 || in a6xx_gpu_init()
2289 config->info->family == ADRENO_7XX_GEN3; in a6xx_gpu_init()
2293 ret = a6xx_set_supported_hw(&pdev->dev, config->info); in a6xx_gpu_init()
2307 a6xx_destroy(&(a6xx_gpu->base.base)); in a6xx_gpu_init()
2316 priv->gpu_clamp_to_idle = true; in a6xx_gpu_init()
2324 a6xx_destroy(&(a6xx_gpu->base.base)); in a6xx_gpu_init()
2331 a6xx_destroy(&(a6xx_gpu->base.base)); in a6xx_gpu_init()
2336 if (gpu->aspace) in a6xx_gpu_init()
2337 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, in a6xx_gpu_init()