561 	gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));  in a6xx_gmu_rpmh_init()
564 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);  in a6xx_gmu_rpmh_init()
565 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);  in a6xx_gmu_rpmh_init()
566 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);  in a6xx_gmu_rpmh_init()
567 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);  in a6xx_gmu_rpmh_init()
568 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);  in a6xx_gmu_rpmh_init()
569 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4,  in a6xx_gmu_rpmh_init()
571 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);  in a6xx_gmu_rpmh_init()
572 	gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
573 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);  in a6xx_gmu_rpmh_init()
574 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);  in a6xx_gmu_rpmh_init()
575 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);  in a6xx_gmu_rpmh_init()
584 		gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0);  in a6xx_gmu_rpmh_init()
585 		gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab);  in a6xx_gmu_rpmh_init()
586 		gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581);  in a6xx_gmu_rpmh_init()
587 		gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2);  in a6xx_gmu_rpmh_init()
588 		gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad);  in a6xx_gmu_rpmh_init()
590 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);  in a6xx_gmu_rpmh_init()
591 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);  in a6xx_gmu_rpmh_init()
592 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);  in a6xx_gmu_rpmh_init()
593 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);  in a6xx_gmu_rpmh_init()
594 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);  in a6xx_gmu_rpmh_init()