42 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);  in a6xx_gmu_irq()
66 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);  in a6xx_hfi_irq()
147 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);  in a6xx_gmu_set_freq()
149 	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,  in a6xx_gmu_set_freq()
156 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);  in a6xx_gmu_set_freq()
220 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);  in a6xx_gmu_start()
226 		gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0);  in a6xx_gmu_start()
228 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);  in a6xx_gmu_start()
231 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);  in a6xx_gmu_start()
247 	gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);  in a6xx_gmu_hfi_start()
328 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);  in a6xx_gmu_set_oob()
341 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);  in a6xx_gmu_set_oob()
361 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);  in a6xx_gmu_clear_oob()
373 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);  in a6xx_sptprac_enable()
398 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);  in a6xx_sptprac_disable()
414 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);  in a6xx_gmu_gfx_rail_on()
419 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);  in a6xx_gmu_gfx_rail_on()
420 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);  in a6xx_gmu_gfx_rail_on()
437 		gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));  in a6xx_gemnoc_workaround()
446 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);  in a6xx_gmu_notify_slumber()
458 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);  in a6xx_gmu_notify_slumber()
476 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_notify_slumber()
485 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));  in a6xx_rpmh_start()
502 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_start()
512 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);  in a6xx_rpmh_stop()
519 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_stop()
672 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);  in a6xx_gmu_power_config()
673 	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
674 	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
680 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);  in a6xx_gmu_power_config()
684 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,  in a6xx_gmu_power_config()
691 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,  in a6xx_gmu_power_config()
792 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);  in a6xx_gmu_fw_start()
793 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);  in a6xx_gmu_fw_start()
800 		gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);  in a6xx_gmu_fw_start()
821 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);  in a6xx_gmu_fw_start()
822 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);  in a6xx_gmu_fw_start()
825 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);  in a6xx_gmu_fw_start()
826 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);  in a6xx_gmu_fw_start()
836 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,  in a6xx_gmu_fw_start()
845 	gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);  in a6xx_gmu_fw_start()
863 		gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid);  in a6xx_gmu_fw_start()
864 		gmu_write(gmu, REG_A7XX_GMU_GENERAL_8,  in a6xx_gmu_fw_start()
868 		gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);  in a6xx_gmu_fw_start()
870 		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,  in a6xx_gmu_fw_start()
917 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);  in a6xx_gmu_irq_disable()
918 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);  in a6xx_gmu_irq_disable()
953 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);  in a6xx_gmu_force_off()
970 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);  in a6xx_gmu_force_off()
971 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_force_off()
977 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);  in a6xx_gmu_force_off()
1058 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);  in a6xx_gmu_resume()
1059 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);  in a6xx_gmu_resume()
1089 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);  in a6xx_gmu_resume()
1090 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);  in a6xx_gmu_resume()