Lines Matching +full:0 +full:x10004000
54 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
116 int ret = 0; in a6xx_gmu_set_freq()
123 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) in a6xx_gmu_set_freq()
147 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); in a6xx_gmu_set_freq()
150 ((3 & 0xf) << 28) | perf_index); in a6xx_gmu_set_freq()
156 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); in a6xx_gmu_set_freq()
211 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); in a6xx_gmu_start()
212 if (val <= 0x20010004) { in a6xx_gmu_start()
213 mask = 0xffffffff; in a6xx_gmu_start()
214 reset_val = 0xbabeface; in a6xx_gmu_start()
216 mask = 0x1ff; in a6xx_gmu_start()
217 reset_val = 0x100; in a6xx_gmu_start()
226 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); in a6xx_gmu_start()
228 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); in a6xx_gmu_start()
231 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); in a6xx_gmu_start()
336 "Timeout waiting for GMU OOB set %s: 0x%x\n", in a6xx_gmu_set_oob()
371 return 0; in a6xx_sptprac_enable()
373 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); in a6xx_sptprac_enable()
376 (val & 0x38) == 0x28, 1, 100); in a6xx_sptprac_enable()
379 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", in a6xx_sptprac_enable()
383 return 0; in a6xx_sptprac_enable()
396 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); in a6xx_sptprac_disable()
398 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); in a6xx_sptprac_disable()
401 (val & 0x04), 100, 10000); in a6xx_sptprac_disable()
404 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", in a6xx_sptprac_disable()
414 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); in a6xx_gmu_gfx_rail_on()
419 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); in a6xx_gmu_gfx_rail_on()
420 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); in a6xx_gmu_gfx_rail_on()
437 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); in a6xx_gemnoc_workaround()
446 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); in a6xx_gmu_notify_slumber()
466 != 0x0f) { in a6xx_gmu_notify_slumber()
476 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_notify_slumber()
502 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_start()
504 return 0; in a6xx_rpmh_start()
519 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_stop()
548 pdc_address_offset = 0x30090; in a6xx_gmu_rpmh_init()
550 pdc_address_offset = 0x300a0; in a6xx_gmu_rpmh_init()
552 pdc_address_offset = 0x30080; in a6xx_gmu_rpmh_init()
565 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); in a6xx_gmu_rpmh_init()
566 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); in a6xx_gmu_rpmh_init()
567 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); in a6xx_gmu_rpmh_init()
568 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); in a6xx_gmu_rpmh_init()
570 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000); in a6xx_gmu_rpmh_init()
571 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); in a6xx_gmu_rpmh_init()
572 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); in a6xx_gmu_rpmh_init()
573 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); in a6xx_gmu_rpmh_init()
574 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); in a6xx_gmu_rpmh_init()
575 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); in a6xx_gmu_rpmh_init()
584 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0); in a6xx_gmu_rpmh_init()
585 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab); in a6xx_gmu_rpmh_init()
586 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581); in a6xx_gmu_rpmh_init()
587 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2); in a6xx_gmu_rpmh_init()
588 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad); in a6xx_gmu_rpmh_init()
590 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init()
591 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init()
592 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init()
593 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init()
594 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); in a6xx_gmu_rpmh_init()
601 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); in a6xx_gmu_rpmh_init()
602 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); in a6xx_gmu_rpmh_init()
603 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); in a6xx_gmu_rpmh_init()
604 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); in a6xx_gmu_rpmh_init()
605 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); in a6xx_gmu_rpmh_init()
609 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); in a6xx_gmu_rpmh_init()
611 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
612 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
614 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
615 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
616 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); in a6xx_gmu_rpmh_init()
618 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
620 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); in a6xx_gmu_rpmh_init()
623 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
624 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); in a6xx_gmu_rpmh_init()
625 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
626 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
629 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
630 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
633 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); in a6xx_gmu_rpmh_init()
635 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); in a6xx_gmu_rpmh_init()
636 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
638 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); in a6xx_gmu_rpmh_init()
642 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); in a6xx_gmu_rpmh_init()
643 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); in a6xx_gmu_rpmh_init()
659 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
660 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
663 #define GMU_PWR_COL_HYST 0x000a1680
672 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); in a6xx_gmu_power_config()
673 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
674 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); in a6xx_gmu_power_config()
680 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); in a6xx_gmu_power_config()
686 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
693 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
699 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, in a6xx_gmu_power_config()
733 u32 itcm_base = 0x00000000; in a6xx_gmu_fw_load()
734 u32 dtcm_base = 0x00040000; in a6xx_gmu_fw_load()
737 dtcm_base = 0x10004000; in a6xx_gmu_fw_load()
741 if (fw_image->size > 0x8000) { in a6xx_gmu_fw_load()
749 return 0; in a6xx_gmu_fw_load()
756 if (blk->size == 0) in a6xx_gmu_fw_load()
773 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", in a6xx_gmu_fw_load()
774 blk->addr, blk->size, blk->data[0]); in a6xx_gmu_fw_load()
778 return 0; in a6xx_gmu_fw_load()
787 u32 chipid = 0; in a6xx_gmu_fw_start()
821 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); in a6xx_gmu_fw_start()
822 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); in a6xx_gmu_fw_start()
829 fence_range_upper = 0x32; in a6xx_gmu_fw_start()
830 fence_range_lower = 0x8a0; in a6xx_gmu_fw_start()
832 fence_range_upper = 0xa; in a6xx_gmu_fw_start()
833 fence_range_lower = 0xa0; in a6xx_gmu_fw_start()
839 FIELD_PREP(GENMASK(17, 0), fence_range_lower)); in a6xx_gmu_fw_start()
845 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); in a6xx_gmu_fw_start()
857 chipid = adreno_gpu->chip_id & 0xffff0000; in a6xx_gmu_fw_start()
858 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ in a6xx_gmu_fw_start()
859 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ in a6xx_gmu_fw_start()
866 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); in a6xx_gmu_fw_start()
901 return 0; in a6xx_gmu_fw_start()
917 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); in a6xx_gmu_irq_disable()
918 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); in a6xx_gmu_irq_disable()
925 u32 val, seqmem_off = 0; in a6xx_gmu_rpmh_off()
953 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); in a6xx_gmu_force_off()
970 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); in a6xx_gmu_force_off()
971 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_force_off()
994 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ in a6xx_gmu_set_initial_freq()
1027 0 /* Hardcode ACD to be disabled for now */); in a6xx_gmu_resume()
1058 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); in a6xx_gmu_resume()
1089 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); in a6xx_gmu_resume()
1136 if (val != 0xf) { in a6xx_gmu_shutdown()
1166 "Unable to slumber GMU: status = 0%x/0%x\n", in a6xx_gmu_shutdown()
1190 return 0; in a6xx_gmu_stop()
1216 return 0; in a6xx_gmu_stop()
1244 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ in a6xx_gmu_memory_alloc()
1245 range_end = 0x80000000; in a6xx_gmu_memory_alloc()
1270 return 0; in a6xx_gmu_memory_alloc()
1277 mmu = msm_iommu_new(gmu->dev, 0); in a6xx_gmu_memory_probe()
1283 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); in a6xx_gmu_memory_probe()
1287 return 0; in a6xx_gmu_memory_probe()
1298 return 0; in a6xx_gmu_get_arc_level()
1302 return 0; in a6xx_gmu_get_arc_level()
1344 for (i = 0; i < freqs_count; i++) { in a6xx_gmu_rpmh_arc_votes_init()
1345 u8 pindex = 0, sindex = 0; in a6xx_gmu_rpmh_arc_votes_init()
1349 for (j = 0; j < pri_count; j++) { in a6xx_gmu_rpmh_arc_votes_init()
1361 for (j = 0; j < pri_count; j++) in a6xx_gmu_rpmh_arc_votes_init()
1372 for (j = 0; j < sec_count; j++) { in a6xx_gmu_rpmh_arc_votes_init()
1382 votes[i] = ((pri[pindex] & 0xffff) << 16) | in a6xx_gmu_rpmh_arc_votes_init()
1386 return 0; in a6xx_gmu_rpmh_arc_votes_init()
1418 int i, index = 0; in a6xx_gmu_build_freq_table()
1431 freqs[index++] = 0; in a6xx_gmu_build_freq_table()
1433 for (i = 0; i < count; i++) { in a6xx_gmu_build_freq_table()
1451 int ret = 0; in a6xx_gmu_pwrlevels_probe()
1494 return 0; in a6xx_gmu_clocks_probe()
1594 return 0; in cxpd_notifier_cb()
1646 return 0; in a6xx_gmu_wrapper_init()
1700 0x60400000, "debug"); in a6xx_gmu_init()
1709 0x60000000, "dummy"); in a6xx_gmu_init()
1717 SZ_16M - SZ_16K, 0x04000, "icache"); in a6xx_gmu_init()
1728 SZ_256K - SZ_16K, 0x04000, "icache"); in a6xx_gmu_init()
1733 SZ_256K - SZ_16K, 0x44000, "dcache"); in a6xx_gmu_init()
1741 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); in a6xx_gmu_init()
1747 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); in a6xx_gmu_init()
1752 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); in a6xx_gmu_init()
1771 gmu->rscc = gmu->mmio + 0x23000; in a6xx_gmu_init()
1778 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) { in a6xx_gmu_init()
1822 return 0; in a6xx_gmu_init()