66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit)  in a5xx_submit_in_rb()  argument
70 	struct msm_ringbuffer *ring = submit->ring;  in a5xx_submit_in_rb()
75 	for (i = 0; i < submit->nr_cmds; i++) {  in a5xx_submit_in_rb()
76 		switch (submit->cmd[i].type) {  in a5xx_submit_in_rb()
80 			if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)  in a5xx_submit_in_rb()
85 			obj = submit->bos[submit->cmd[i].idx].obj;  in a5xx_submit_in_rb()
86 			dwords = submit->cmd[i].size;  in a5xx_submit_in_rb()
114 	a5xx_gpu->last_seqno[ring->id] = submit->seqno;  in a5xx_submit_in_rb()
123 	ring->memptrs->fence = submit->seqno;  in a5xx_submit_in_rb()
127 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)  in a5xx_submit()  argument
131 	struct msm_ringbuffer *ring = submit->ring;  in a5xx_submit()
134 	if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) {  in a5xx_submit()
136 		a5xx_submit_in_rb(gpu, submit);  in a5xx_submit()
149 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
150 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
169 	for (i = 0; i < submit->nr_cmds; i++) {  in a5xx_submit()
170 		switch (submit->cmd[i].type) {  in a5xx_submit()
174 			if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)  in a5xx_submit()
179 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a5xx_submit()
180 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a5xx_submit()
181 			OUT_RING(ring, submit->cmd[i].size);  in a5xx_submit()
215 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
216 	a5xx_gpu->last_seqno[ring->id] = submit->seqno;  in a5xx_submit()
227 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
1701 		.submit = a5xx_submit,