Lines Matching +full:0 +full:x0001ffff
75 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit_in_rb()
97 for (i = 0; i < dwords; i++) { in a5xx_submit_in_rb()
132 unsigned int i, ibs = 0; in a5xx_submit()
135 gpu->cur_ctx_seqno = 0; in a5xx_submit()
141 OUT_RING(ring, 0x02); in a5xx_submit()
145 OUT_RING(ring, 0); in a5xx_submit()
162 OUT_RING(ring, 0x0); in a5xx_submit()
166 OUT_RING(ring, 0x02); in a5xx_submit()
169 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit()
193 if ((ibs % 32) == 0) in a5xx_submit()
198 * Write the render mode to NULL (0) to indicate to the CP that the IBs in a5xx_submit()
203 OUT_RING(ring, 0); in a5xx_submit()
204 OUT_RING(ring, 0); in a5xx_submit()
205 OUT_RING(ring, 0); in a5xx_submit()
206 OUT_RING(ring, 0); in a5xx_submit()
207 OUT_RING(ring, 0); in a5xx_submit()
211 OUT_RING(ring, 0x01); in a5xx_submit()
233 * write the value of dword[3] to on preemption complete. Write 0 to in a5xx_submit()
236 OUT_RING(ring, 0x00); in a5xx_submit()
237 OUT_RING(ring, 0x00); in a5xx_submit()
238 /* Data value - not used if the address above is 0 */ in a5xx_submit()
239 OUT_RING(ring, 0x01); in a5xx_submit()
240 /* Set bit 0 to trigger an interrupt on preempt complete */ in a5xx_submit()
241 OUT_RING(ring, 0x01); in a5xx_submit()
254 {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
255 {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
256 {REG_A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},
257 {REG_A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},
258 {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
259 {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
260 {REG_A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},
261 {REG_A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},
262 {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
263 {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
264 {REG_A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},
265 {REG_A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},
266 {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
267 {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
268 {REG_A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
269 {REG_A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
270 {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
271 {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
272 {REG_A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},
273 {REG_A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},
274 {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
275 {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
276 {REG_A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
277 {REG_A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
278 {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
279 {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
280 {REG_A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222},
281 {REG_A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222},
282 {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
283 {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
284 {REG_A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
285 {REG_A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
286 {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
287 {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
288 {REG_A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
289 {REG_A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
290 {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
291 {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
292 {REG_A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777},
293 {REG_A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777},
294 {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
295 {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
296 {REG_A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
297 {REG_A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
298 {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
299 {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
300 {REG_A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
301 {REG_A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
302 {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
303 {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
304 {REG_A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111},
305 {REG_A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111},
306 {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
307 {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
308 {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
309 {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
310 {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
311 {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
312 {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
313 {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
314 {REG_A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
315 {REG_A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
316 {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
317 {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
318 {REG_A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222},
319 {REG_A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222},
320 {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
321 {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
322 {REG_A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},
323 {REG_A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},
324 {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
325 {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
326 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
327 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
328 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},
329 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404},
330 {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
331 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
332 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
333 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002},
334 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002},
335 {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
336 {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
337 {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
338 {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
339 {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
340 {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
341 {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
342 {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
343 {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
344 {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
345 {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}
347 {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
348 {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
349 {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
350 {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
351 {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
352 {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
353 {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
354 {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
355 {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
356 {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
357 {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
358 {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
359 {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
360 {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
361 {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
362 {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
363 {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
364 {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},
365 {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
366 {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
367 {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
368 {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
369 {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
370 {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
371 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
372 {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
373 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
374 {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
375 {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
376 {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
377 {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
378 {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
379 {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
380 {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
381 {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
382 {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
383 {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
384 {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
386 {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
387 {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
388 {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
389 {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
390 {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
391 {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
392 {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
393 {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
394 {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
395 {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
396 {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
397 {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
398 {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
399 {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
400 {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
401 {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
402 {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
403 {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
404 {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
405 {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
406 {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
407 {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
408 {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
409 {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
410 {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
411 {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
412 {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
413 {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
414 {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
415 {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
416 {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
417 {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
418 {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
419 {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
420 {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
421 {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
422 {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
423 {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
424 {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
425 {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
426 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
427 {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
428 {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
429 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
430 {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
431 {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
432 {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
433 {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
434 {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
435 {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
436 {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
437 {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
438 {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
439 {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
440 {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
441 {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
462 for (i = 0; i < sz; i++) in a5xx_set_hwcg()
464 state ? regs[i].value : 0); in a5xx_set_hwcg()
467 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
468 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
471 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
472 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
478 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_me_init()
482 OUT_RING(ring, 0x0000002F); in a5xx_me_init()
485 OUT_RING(ring, 0x00000003); in a5xx_me_init()
488 OUT_RING(ring, 0x20000000); in a5xx_me_init()
491 OUT_RING(ring, 0x00000000); in a5xx_me_init()
492 OUT_RING(ring, 0x00000000); in a5xx_me_init()
501 OUT_RING(ring, 0x0000000B); in a5xx_me_init()
504 OUT_RING(ring, 0x00000001); in a5xx_me_init()
507 OUT_RING(ring, 0x00000000); in a5xx_me_init()
510 OUT_RING(ring, 0x00000000); in a5xx_me_init()
511 OUT_RING(ring, 0x00000000); in a5xx_me_init()
514 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_me_init()
521 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_preempt_start()
524 return 0; in a5xx_preempt_start()
528 OUT_RING(ring, 0); in a5xx_preempt_start()
540 OUT_RING(ring, 0x00); in a5xx_preempt_start()
543 OUT_RING(ring, 0x01); in a5xx_preempt_start()
546 OUT_RING(ring, 0x01); in a5xx_preempt_start()
550 OUT_RING(ring, 0x00); in a5xx_preempt_start()
551 OUT_RING(ring, 0x00); in a5xx_preempt_start()
552 OUT_RING(ring, 0x01); in a5xx_preempt_start()
553 OUT_RING(ring, 0x01); in a5xx_preempt_start()
558 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_preempt_start()
570 * If the lowest nibble is 0xa that is an indication that this microcode in a5xx_ucode_check_version()
574 if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) in a5xx_ucode_check_version()
637 return 0; in a5xx_ucode_load()
640 #define SCM_GPU_ZAP_SHADER_RESUME 0
652 return 0; in a5xx_zap_shader_resume()
700 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
704 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
707 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
710 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
719 0xF0000000); in a5xx_hw_init()
721 0xFFFFFFFF); in a5xx_hw_init()
723 0xFFFFFFFF); in a5xx_hw_init()
725 0xFFFFFFFF); in a5xx_hw_init()
727 0xFFFFFFFF); in a5xx_hw_init()
729 0xFFFFFFFF); in a5xx_hw_init()
731 0xFFFFFFFF); in a5xx_hw_init()
733 0xFFFFFFFF); in a5xx_hw_init()
738 (1 << 30) | 0xFFFF); in a5xx_hw_init()
741 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); in a5xx_hw_init()
750 gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); in a5xx_hw_init()
753 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
754 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
755 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
756 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
758 /* Set the GMEM VA range (0 to gpu->gmem) */ in a5xx_hw_init()
759 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); in a5xx_hw_init()
760 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); in a5xx_hw_init()
762 0x00100000 + adreno_gpu->info->gmem - 1); in a5xx_hw_init()
763 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); in a5xx_hw_init()
767 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); in a5xx_hw_init()
770 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
772 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); in a5xx_hw_init()
773 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); in a5xx_hw_init()
774 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); in a5xx_hw_init()
776 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); in a5xx_hw_init()
778 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); in a5xx_hw_init()
780 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
781 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); in a5xx_hw_init()
782 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); in a5xx_hw_init()
788 (0x100 << 11 | 0x100 << 22)); in a5xx_hw_init()
792 (0x200 << 11 | 0x200 << 22)); in a5xx_hw_init()
795 (0x400 << 11 | 0x300 << 22)); in a5xx_hw_init()
798 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); in a5xx_hw_init()
807 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); in a5xx_hw_init()
813 gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); in a5xx_hw_init()
816 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); in a5xx_hw_init()
825 * bit[11] of RB_DBG_ECO_CNTL need to be set to 0, default is 1 in a5xx_hw_init()
829 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0); in a5xx_hw_init()
834 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); in a5xx_hw_init()
847 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); in a5xx_hw_init()
850 gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); in a5xx_hw_init()
853 gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); in a5xx_hw_init()
854 gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); in a5xx_hw_init()
855 gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); in a5xx_hw_init()
856 gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); in a5xx_hw_init()
857 gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); in a5xx_hw_init()
858 gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); in a5xx_hw_init()
868 gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); in a5xx_hw_init()
869 gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); in a5xx_hw_init()
870 gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); in a5xx_hw_init()
871 gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); in a5xx_hw_init()
874 gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); in a5xx_hw_init()
875 gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); in a5xx_hw_init()
878 gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); in a5xx_hw_init()
879 gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); in a5xx_hw_init()
882 gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); in a5xx_hw_init()
886 ADRENO_PROTECT_RW(0x10000, 0x8000)); in a5xx_hw_init()
888 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); in a5xx_hw_init()
894 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000); in a5xx_hw_init()
895 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a5xx_hw_init()
898 gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
899 gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
900 gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
901 gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
902 gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
903 gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
904 gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
905 gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
906 gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
907 gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
908 gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
909 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
917 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); in a5xx_hw_init()
918 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); in a5xx_hw_init()
932 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
946 shadowptr(a5xx_gpu, gpu->rb[0])); in a5xx_hw_init()
955 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
969 OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1); in a5xx_hw_init()
970 OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT)); in a5xx_hw_init()
972 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
973 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
987 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in a5xx_hw_init()
988 OUT_RING(gpu->rb[0], 0x00000000); in a5xx_hw_init()
990 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
991 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
1002 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); in a5xx_hw_init()
1010 return 0; in a5xx_hw_init()
1019 for (i = 0; i < 8; i++) { in a5xx_recover()
1029 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); in a5xx_recover()
1095 gpu->name, __builtin_return_address(0), in a5xx_idle()
1131 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); in a5xx_cp_err_irq()
1141 dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", in a5xx_cp_err_irq()
1146 dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", in a5xx_cp_err_irq()
1156 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", in a5xx_cp_err_irq()
1158 (val & 0xFFFFF) >> 2, val); in a5xx_cp_err_irq()
1169 "CP | AHB error | addr=%X access=%s error=%d | status=0x%8.8X\n", in a5xx_cp_err_irq()
1170 status & 0xFFFFF, access[(status >> 24) & 0xF], in a5xx_cp_err_irq()
1181 "RBBM | AHB bus error | %s | addr=0x%X | ports=0x%X:0x%X\n", in a5xx_rbbm_err_irq()
1183 (val & 0xFFFFF) >> 2, (val >> 20) & 0x3, in a5xx_rbbm_err_irq()
1184 (val >> 24) & 0xF); in a5xx_rbbm_err_irq()
1198 dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1202 dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1206 dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1222 dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", in a5xx_uche_err_irq()
1246 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, in a5xx_fault_detect_irq()
1314 0x0000, 0x0002, 0x0004, 0x0020, 0x0022, 0x0026, 0x0029, 0x002B,
1315 0x002E, 0x0035, 0x0038, 0x0042, 0x0044, 0x0044, 0x0047, 0x0095,
1316 0x0097, 0x00BB, 0x03A0, 0x0464, 0x0469, 0x046F, 0x04D2, 0x04D3,
1317 0x04E0, 0x0533, 0x0540, 0x0555, 0x0800, 0x081A, 0x081F, 0x0841,
1318 0x0860, 0x0860, 0x0880, 0x08A0, 0x0B00, 0x0B12, 0x0B15, 0x0B28,
1319 0x0B78, 0x0B7F, 0x0BB0, 0x0BBD, 0x0BC0, 0x0BC6, 0x0BD0, 0x0C53,
1320 0x0C60, 0x0C61, 0x0C80, 0x0C82, 0x0C84, 0x0C85, 0x0C90, 0x0C98,
1321 0x0CA0, 0x0CA0, 0x0CB0, 0x0CB2, 0x2180, 0x2185, 0x2580, 0x2585,
1322 0x0CC1, 0x0CC1, 0x0CC4, 0x0CC7, 0x0CCC, 0x0CCC, 0x0CD0, 0x0CD8,
1323 0x0CE0, 0x0CE5, 0x0CE8, 0x0CE8, 0x0CEC, 0x0CF1, 0x0CFB, 0x0D0E,
1324 0x2100, 0x211E, 0x2140, 0x2145, 0x2500, 0x251E, 0x2540, 0x2545,
1325 0x0D10, 0x0D17, 0x0D20, 0x0D23, 0x0D30, 0x0D30, 0x20C0, 0x20C0,
1326 0x24C0, 0x24C0, 0x0E40, 0x0E43, 0x0E4A, 0x0E4A, 0x0E50, 0x0E57,
1327 0x0E60, 0x0E7C, 0x0E80, 0x0E8E, 0x0E90, 0x0E96, 0x0EA0, 0x0EA8,
1328 0x0EB0, 0x0EB2, 0xE140, 0xE147, 0xE150, 0xE187, 0xE1A0, 0xE1A9,
1329 0xE1B0, 0xE1B6, 0xE1C0, 0xE1C7, 0xE1D0, 0xE1D1, 0xE200, 0xE201,
1330 0xE210, 0xE21C, 0xE240, 0xE268, 0xE000, 0xE006, 0xE010, 0xE09A,
1331 0xE0A0, 0xE0A4, 0xE0AA, 0xE0EB, 0xE100, 0xE105, 0xE380, 0xE38F,
1332 0xE3B0, 0xE3B0, 0xE400, 0xE405, 0xE408, 0xE4E9, 0xE4F0, 0xE4F0,
1333 0xE280, 0xE280, 0xE282, 0xE2A3, 0xE2A5, 0xE2C2, 0xE940, 0xE947,
1334 0xE950, 0xE987, 0xE9A0, 0xE9A9, 0xE9B0, 0xE9B6, 0xE9C0, 0xE9C7,
1335 0xE9D0, 0xE9D1, 0xEA00, 0xEA01, 0xEA10, 0xEA1C, 0xEA40, 0xEA68,
1336 0xE800, 0xE806, 0xE810, 0xE89A, 0xE8A0, 0xE8A4, 0xE8AA, 0xE8EB,
1337 0xE900, 0xE905, 0xEB80, 0xEB8F, 0xEBB0, 0xEBB0, 0xEC00, 0xEC05,
1338 0xEC08, 0xECE9, 0xECF0, 0xECF0, 0xEA80, 0xEA80, 0xEA82, 0xEAA3,
1339 0xEAA5, 0xEAC2, 0xA800, 0xA800, 0xA820, 0xA828, 0xA840, 0xA87D,
1340 0XA880, 0xA88D, 0xA890, 0xA8A3, 0xA8D0, 0xA8D8, 0xA8E0, 0xA8F5,
1341 0xAC60, 0xAC60, ~0,
1364 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); in a5xx_pm_resume()
1367 gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0); in a5xx_pm_resume()
1368 return 0; in a5xx_pm_resume()
1372 gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1387 gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1401 u32 mask = 0xf; in a5xx_pm_suspend()
1407 mask = 0x7; in a5xx_pm_suspend()
1414 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); in a5xx_pm_suspend()
1421 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); in a5xx_pm_suspend()
1422 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); in a5xx_pm_suspend()
1430 for (i = 0; i < gpu->nr_rings; i++) in a5xx_pm_suspend()
1431 a5xx_gpu->shadow[i] = 0; in a5xx_pm_suspend()
1433 return 0; in a5xx_pm_suspend()
1440 return 0; in a5xx_get_timestamp()
1480 val & 0x04, 100, 10000); in a5xx_crashdumper_run()
1493 { 0x35, 0xe00, 0x32 }, /* HSLQ non-context */
1494 { 0x31, 0x2080, 0x1 }, /* HLSQ 2D context 0 */
1495 { 0x33, 0x2480, 0x1 }, /* HLSQ 2D context 1 */
1496 { 0x32, 0xe780, 0x62 }, /* HLSQ 3D context 0 */
1497 { 0x34, 0xef80, 0x62 }, /* HLSQ 3D context 1 */
1498 { 0x3f, 0x0ec0, 0x40 }, /* SP non-context */
1499 { 0x3d, 0x2040, 0x1 }, /* SP 2D context 0 */
1500 { 0x3b, 0x2440, 0x1 }, /* SP 2D context 1 */
1501 { 0x3e, 0xe580, 0x170 }, /* SP 3D context 0 */
1502 { 0x3c, 0xed80, 0x170 }, /* SP 3D context 1 */
1503 { 0x3a, 0x0f00, 0x1c }, /* TP non-context */
1504 { 0x38, 0x2000, 0xa }, /* TP 2D context 0 */
1505 { 0x36, 0x2400, 0xa }, /* TP 2D context 1 */
1506 { 0x39, 0xe700, 0x80 }, /* TP 3D context 0 */
1507 { 0x37, 0xef00, 0x80 }, /* TP 3D context 1 */
1513 struct a5xx_crashdumper dumper = { 0 }; in a5xx_gpu_state_get_hlsq_regs()
1514 u32 offset, count = 0; in a5xx_gpu_state_get_hlsq_regs()
1521 /* The script will be written at offset 0 */ in a5xx_gpu_state_get_hlsq_regs()
1528 for (i = 0; i < ARRAY_SIZE(a5xx_hlsq_aperture_regs); i++) in a5xx_gpu_state_get_hlsq_regs()
1536 for (i = 0; i < ARRAY_SIZE(a5xx_hlsq_aperture_regs); i++) { in a5xx_gpu_state_get_hlsq_regs()
1553 *ptr++ = 0; in a5xx_gpu_state_get_hlsq_regs()
1554 *ptr++ = 0; in a5xx_gpu_state_get_hlsq_regs()
1626 u32 pos = 0; in a5xx_show()
1641 for (i = 0; i < ARRAY_SIZE(a5xx_hlsq_aperture_regs); i++) { in a5xx_show()
1645 for (j = 0; j < c; j++, pos++, o++) { in a5xx_show()
1651 * 0xdeadbeef in a5xx_show()
1653 if (a5xx_state->hlsqregs[pos] == 0xdeadbeef) in a5xx_show()
1656 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", in a5xx_show()
1732 val = 0x80; in check_speed_bin()
1777 a5xx_gpu->lm_leakage = 0x4E001A; in a5xx_gpu_init()
1805 adreno_gpu->ubwc_config.macrotile_mode = 0; in a5xx_gpu_init()
1806 adreno_gpu->ubwc_config.ubwc_swizzle = 0x7; in a5xx_gpu_init()