64 #define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */
65 #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
66 #define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbb offset in data sheet */
67 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
68 #define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */
69 #define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */
78 	.video_prog_mode = 0xff,
79 	.video_mode = 0x13,
80 	.sch_adjust = 0x28,
81 	.yc_delay = 0x343,
89 	.video_contrast = 0,
90 	.video_brightness = 0,
91 	.video_hue = 0,
92 	.analog_sync_adj = 0x8080,
101 	.macv_max_amp = 0xb,
102 	.video_prog_mode = 0xf0,
103 	.video_mode = 0x8,
104 	.sch_adjust = 0x20,
105 	.yc_delay = 0x333,
114 	.video_brightness = 0,
115 	.video_hue = 0,
116 	.analog_sync_adj = 0x9c00,
197 		.macv_max_amp = 0xb,
198 		.video_prog_mode = 0xf0,
199 		.video_mode = 0x8,
200 		.sch_adjust = 0x20,
201 		.yc_delay = 0,
217 		.macv_max_amp = 0x7,
218 		.video_prog_mode = 0xff,
219 		.video_mode = 0x13,
220 		.sch_adjust = 0x28,
221 		.yc_delay = 0x333,
233 		.dvi_settings = 0x21,
234 		.video_mode = 0x4000,
235 		.video_mode_adv = 0x9,
236 		.video_prog_mode = 0,
242 		.video_filt_ctrl = 0x2052,
248 		.hspuls_begin = 0x22,
249 		.hspuls_end = 0xa0,
251 		.vspuls_begin = 0,
253 		.vspuls_bline = 0,
267 		.vso_bline = 0,
271 		.sy2_val = 0x1d8,
279 		.dvi_settings = 0x21,
280 		.video_mode = 0x4000,
281 		.video_mode_adv = 0x9,
282 		.video_prog_mode = 0,
288 		.video_filt_ctrl = 0x52,
294 		.hspuls_begin = 0,
295 		.hspuls_end = 0x80,
297 		.vspuls_begin = 0,
299 		.vspuls_bline = 0,
309 		.hso_begin = 0x80,
310 		.hso_end = 0,
311 		.vso_begin = 0,
313 		.vso_bline = 0,
317 		.sy2_val = 0x1d8,
325 		.dvi_settings = 0x2029,
326 		.video_mode = 0x4040,
327 		.video_mode_adv = 0x19,
356 		.vso_bline = 0,
367 		.dvi_settings = 0x202d,
368 		.video_mode = 0x4040,
369 		.video_mode_adv = 0x19,
370 		.video_prog_mode = 0x100,
372 		.video_sync_mode = 0x407,
374 		.video_yc_dly = 0,
401 		.vso_bline = 0,
412 		.dvi_settings = 0x2029,
413 		.video_mode = 0x5ffc,
414 		.video_mode_adv = 0x19,
415 		.video_prog_mode = 0x100,
417 		.video_sync_mode = 0x207,
422 		.video_ofld_voav_ofst = 0x11,
432 		.vspuls_bline = 0,
442 		.eqpuls_bline = 0,
450 		.vso_bline = 0,
461 		.dvi_settings = 0x202d,
462 		.video_mode = 0x5ffc,
463 		.video_mode_adv = 0x19,
464 		.video_prog_mode = 0x100,
466 		.video_sync_mode = 0x7,
471 		.video_ofld_voav_ofst = 0x11,
481 		.vspuls_bline = 0,
491 		.eqpuls_bline = 0,
499 		.vso_bline = 0,
510 		.dvi_settings = 0xd,
511 		.video_mode = 0x4040,
512 		.video_mode_adv = 0x18,
513 		.video_prog_mode = 0x100,
515 		.video_sync_mode = 0x7,
517 		.video_yc_dly = 0,
521 		.video_filt_ctrl = 0x1052,
532 		.vspuls_bline = 0,
540 		.eqpuls_bline = 0,
548 		.vso_bline = 0,
559 		.dvi_settings = 0x1,
560 		.video_mode = 0x4040,
561 		.video_mode_adv = 0x18,
562 		.video_prog_mode = 0x100,
567 		.video_filt_ctrl = 0x1052,
578 		.vspuls_bline = 0,
592 		.vso_bline = 0,
603 		.dvi_settings = 0xd,
604 		.video_mode = 0x4040,
605 		.video_mode_adv = 0x18,
606 		.video_prog_mode = 0x100,
608 		.video_sync_mode = 0x7,
610 		.video_yc_dly = 0,
624 		.vspuls_bline = 0,
632 		.eqpuls_bline = 0,
640 		.vso_bline = 0,
651 		.dvi_settings = 0x1,
652 		.video_mode = 0x4040,
653 		.video_mode_adv = 0x18,
654 		.video_prog_mode = 0x100,
659 		.video_filt_ctrl = 0x1052,
670 		.vspuls_bline = 0,
684 		.vso_bline = 0,
695 		.dvi_settings = 0x1,
696 		.video_mode = 0x4040,
697 		.video_mode_adv = 0x8,
701 		.video_filt_ctrl = 0x1000,
712 		.vspuls_bline = 0,
737 		.dvi_settings = 0x1,
738 		.video_mode = 0x4040,
739 		.video_mode_adv = 0x8,
743 		.video_filt_ctrl = 0x1000,
754 		.vspuls_bline = 0,
779 		.dvi_settings = 0x1,
780 		.video_mode = 0x4040,
781 		.video_mode_adv = 0x8,
785 		.video_filt_ctrl = 0x1000,
796 		.vspuls_bline = 0,
845 	{ 0, NULL}, /* sentinel */
898 	memset(dmt_mode, 0, sizeof(*dmt_mode));  in meson_venc_hdmi_get_dmt_vmode()
900 	dmt_mode->encp.dvi_settings = 0x21;  in meson_venc_hdmi_get_dmt_vmode()
901 	dmt_mode->encp.video_mode = 0x4040;  in meson_venc_hdmi_get_dmt_vmode()
902 	dmt_mode->encp.video_mode_adv = 0x18;  in meson_venc_hdmi_get_dmt_vmode()
910 	dmt_mode->encp.hso_begin = 0;  in meson_venc_hdmi_get_dmt_vmode()
914 	dmt_mode->encp.vso_bline = 0;  in meson_venc_hdmi_get_dmt_vmode()
961 	unsigned long total_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
962 	unsigned long active_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
963 	unsigned long front_porch_venc = 0;  in meson_venc_hdmi_mode_set()
964 	unsigned long hsync_pixels_venc = 0;  in meson_venc_hdmi_mode_set()
965 	unsigned long de_h_begin = 0;  in meson_venc_hdmi_mode_set()
966 	unsigned long de_h_end = 0;  in meson_venc_hdmi_mode_set()
967 	unsigned long de_v_begin_even = 0;  in meson_venc_hdmi_mode_set()
968 	unsigned long de_v_end_even = 0;  in meson_venc_hdmi_mode_set()
969 	unsigned long de_v_begin_odd = 0;  in meson_venc_hdmi_mode_set()
970 	unsigned long de_v_end_odd = 0;  in meson_venc_hdmi_mode_set()
971 	unsigned long hs_begin = 0;  in meson_venc_hdmi_mode_set()
972 	unsigned long hs_end = 0;  in meson_venc_hdmi_mode_set()
973 	unsigned long vs_adjust = 0;  in meson_venc_hdmi_mode_set()
974 	unsigned long vs_bline_evn = 0;  in meson_venc_hdmi_mode_set()
975 	unsigned long vs_eline_evn = 0;  in meson_venc_hdmi_mode_set()
976 	unsigned long vs_bline_odd = 0;  in meson_venc_hdmi_mode_set()
977 	unsigned long vs_eline_odd = 0;  in meson_venc_hdmi_mode_set()
978 	unsigned long vso_begin_evn = 0;  in meson_venc_hdmi_mode_set()
979 	unsigned long vso_begin_odd = 0;  in meson_venc_hdmi_mode_set()
1045 	writel_bits_relaxed(0xff, 0xff,  in meson_venc_hdmi_mode_set()
1048 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));  in meson_venc_hdmi_mode_set()
1049 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));  in meson_venc_hdmi_mode_set()
1056 		writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,  in meson_venc_hdmi_mode_set()
1063 		writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));  in meson_venc_hdmi_mode_set()
1066 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));  in meson_venc_hdmi_mode_set()
1067 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));  in meson_venc_hdmi_mode_set()
1094 		 * Demux shifting 0x2  in meson_venc_hdmi_mode_set()
1110 		writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));  in meson_venc_hdmi_mode_set()
1118 		writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));  in meson_venc_hdmi_mode_set()
1126 		 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y  in meson_venc_hdmi_mode_set()
1129 			       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),  in meson_venc_hdmi_mode_set()
1193 			vs_adjust  = 0;  in meson_venc_hdmi_mode_set()
1436 			de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)  in meson_venc_hdmi_mode_set()
1456 			vs_adjust  = 0;  in meson_venc_hdmi_mode_set()
1563 	0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
1587 	writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0,  in meson_encl_set_gamma_table()
1596 		       FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0),  in meson_encl_set_gamma_table()
1599 	for (i = 0; i < 256; i++) {  in meson_encl_set_gamma_table()
1615 		       FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0x23),  in meson_encl_set_gamma_table()
1651 	hso_begin = 0;  in meson_venc_mipi_dsi_mode_set()
1653 	vso_begin = 0;  in meson_venc_mipi_dsi_mode_set()
1654 	vso_end = 0;  in meson_venc_mipi_dsi_mode_set()
1655 	vso_bline = 0;  in meson_venc_mipi_dsi_mode_set()
1660 	writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));  in meson_venc_mipi_dsi_mode_set()
1686 	writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL));  in meson_venc_mipi_dsi_mode_set()
1687 	writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y));  in meson_venc_mipi_dsi_mode_set()
1688 	writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB));  in meson_venc_mipi_dsi_mode_set()
1689 	writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR));  in meson_venc_mipi_dsi_mode_set()
1691 	writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0,  in meson_venc_mipi_dsi_mode_set()
1696 	writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR));  in meson_venc_mipi_dsi_mode_set()
1697 	writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */  in meson_venc_mipi_dsi_mode_set()
1721 	writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR));  in meson_venc_mipi_dsi_mode_set()
1744 	writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR));  in meson_venc_mipi_dsi_mode_set()
1753 	writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR));  in meson_venc_mipi_dsi_mode_set()
1770 	writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,  in meson_venci_cvbs_mode_set()
1777 	writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));  in meson_venci_cvbs_mode_set()
1780 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));  in meson_venci_cvbs_mode_set()
1781 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));  in meson_venci_cvbs_mode_set()
1808 	 * Demux shifting 0x2  in meson_venci_cvbs_mode_set()
1823 	writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));  in meson_venci_cvbs_mode_set()
1825 	/* 0x3 Y, C, and Component Y delay */  in meson_venci_cvbs_mode_set()
1845 	writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));  in meson_venci_cvbs_mode_set()
1848 	writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));  in meson_venci_cvbs_mode_set()
1856 	 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y  in meson_venci_cvbs_mode_set()
1859 		       ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),  in meson_venci_cvbs_mode_set()
1863 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));  in meson_venci_cvbs_mode_set()
1896 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));  in meson_venci_cvbs_mode_set()
1897 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));  in meson_venci_cvbs_mode_set()
1898 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));  in meson_venci_cvbs_mode_set()
1899 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));  in meson_venci_cvbs_mode_set()
1900 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));  in meson_venci_cvbs_mode_set()
1901 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));  in meson_venci_cvbs_mode_set()
1910 	/* Select ENCI DACs 0, 1, 4, and 5 */  in meson_venci_cvbs_mode_set()
1911 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));  in meson_venci_cvbs_mode_set()
1912 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));  in meson_venci_cvbs_mode_set()
1931 	writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));  in meson_venci_cvbs_mode_set()
1933 	/* 0 in Macrovision register 0 */  in meson_venci_cvbs_mode_set()
1934 	writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));  in meson_venci_cvbs_mode_set()
1965 	regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0);  in meson_venc_disable_vsync()
1966 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));  in meson_venc_disable_vsync()
1973 		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);  in meson_venc_init()
1976 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);  in meson_venc_init()
1981 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));  in meson_venc_init()
1984 	regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);  in meson_venc_init()
1988 			    VPU_HDMI_ENCP_DATA_TO_HDMI, 0,  in meson_venc_init()
1992 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));  in meson_venc_init()
1993 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));  in meson_venc_init()
1994 	writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));  in meson_venc_init()