Lines Matching refs:HHI_VID_CLK_DIV

66 #define HHI_VID_CLK_DIV		0x164 /* 0x59 offset in data sheet */  macro
314 	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_venci_cvbs_clock_config()
887 	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
950 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
954 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
964 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
968 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
978 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
982 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
992 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
996 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
1006 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()
1010 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,  in meson_vclk_set()