Lines Matching +full:data +full:- +full:sheet
1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
33 * | | | | | |--ENCI
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
36 * --VCLK2-| |--VDAC
37 * |_____|--HDMI-TX
50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
54 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
60 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
66 #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
74 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
84 #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
96 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
97 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
99 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
101 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
102 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
103 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
104 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
105 #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
106 #define HHI_HDMI_PLL_CNTL7 0x338 /* 0xce offset in data sheet */
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
223 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
231 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
255 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
262 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c); in meson_venci_cvbs_clock_config()
263 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_venci_cvbs_clock_config()
264 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); in meson_venci_cvbs_clock_config()
267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
273 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); in meson_venci_cvbs_clock_config()
278 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_venci_cvbs_clock_config()
279 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00); in meson_venci_cvbs_clock_config()
280 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290); in meson_venci_cvbs_clock_config()
281 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); in meson_venci_cvbs_clock_config()
282 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000); in meson_venci_cvbs_clock_config()
283 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7); in meson_venci_cvbs_clock_config()
284 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
287 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
299 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
300 VCLK2_DIV_MASK, (55 - 1)); in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
314 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_venci_cvbs_clock_config()
317 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
321 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
335 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
338 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
497 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); in meson_hdmi_pll_set_params()
499 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
502 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
504 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_hdmi_pll_set_params()
505 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_hdmi_pll_set_params()
506 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_hdmi_pll_set_params()
507 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_hdmi_pll_set_params()
510 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
514 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
518 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); in meson_hdmi_pll_set_params()
519 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
520 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); in meson_hdmi_pll_set_params()
521 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); in meson_hdmi_pll_set_params()
522 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_hdmi_pll_set_params()
523 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); in meson_hdmi_pll_set_params()
526 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
528 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
532 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()
535 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); in meson_hdmi_pll_set_params()
539 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
542 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
543 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_hdmi_pll_set_params()
548 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
550 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
553 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
555 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
558 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); in meson_hdmi_pll_set_params()
559 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000); in meson_hdmi_pll_set_params()
561 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00); in meson_hdmi_pll_set_params()
562 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290); in meson_hdmi_pll_set_params()
563 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000); in meson_hdmi_pll_set_params()
564 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000); in meson_hdmi_pll_set_params()
569 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
572 /* UN-Reset PLL */ in meson_hdmi_pll_set_params()
573 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
577 if (!regmap_read_poll_timeout(priv->hhi, in meson_hdmi_pll_set_params()
587 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
591 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
594 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
598 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
602 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
605 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
609 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
613 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
616 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
625 /* The GXBB PLL has a /2 pre-multiplier */ in meson_hdmi_pll_get_m()
645 /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */ in meson_hdmi_pll_get_frac()
663 frac -= frac_m; in meson_hdmi_pll_get_frac()
665 return min((u16)frac, (u16)(frac_max - 1)); in meson_hdmi_pll_get_frac()
729 if (priv->limits) { in meson_vclk_dmt_supported_freq()
730 if (priv->limits->max_hdmi_phy_freq && in meson_vclk_dmt_supported_freq()
731 freq > priv->limits->max_hdmi_phy_freq) in meson_vclk_dmt_supported_freq()
781 if (priv->limits) { in meson_vclk_vic_supported_freq()
782 if (priv->limits->max_hdmi_phy_freq && in meson_vclk_vic_supported_freq()
783 phy_freq > priv->limits->max_hdmi_phy_freq) in meson_vclk_vic_supported_freq()
816 /* Set HDMI-TX sys clock */ in meson_vclk_set()
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
885 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
887 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
888 VCLK_DIV_MASK, vclk_div - 1); in meson_vclk_set()
890 /* Set HDMI-TX source */ in meson_vclk_set()
894 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
897 /* select vclk_div1 for HDMI-TX */ in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
903 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
906 /* select vclk_div2 for HDMI-TX */ in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
912 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
915 /* select vclk_div4 for HDMI-TX */ in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
921 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
924 /* select vclk_div6 for HDMI-TX */ in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
930 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
933 /* select vclk_div12 for HDMI-TX */ in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
938 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
945 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
950 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
954 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
959 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
964 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
968 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
973 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
978 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
982 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
987 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
992 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
996 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1001 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
1006 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1010 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1017 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
1021 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
1024 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); in meson_vclk_set()
1043 * - automatic PLL freq + OD management in meson_vclk_setup()
1044 * - vid_pll_div = VID_PLL_DIV_5 in meson_vclk_setup()
1045 * - vclk_div = 2 in meson_vclk_setup()
1046 * - hdmi_tx_div = 1 in meson_vclk_setup()
1047 * - venc_div = 1 in meson_vclk_setup()
1048 * - encp encoder in meson_vclk_setup()
1058 pr_err("Fatal Error, invalid HDMI-TX freq %d\n", in meson_vclk_setup()