Lines Matching +full:pixel +full:- +full:format
1 // SPDX-License-Identifier: GPL-2.0+
30 * - basic AFBC buffer for RGB32 only, thus YTR feature is mandatory
31 * - SPARSE layout and SPLIT layout
32 * - only 16x16 superblock
35 * decoded pixel stream to the OSD1 Plane pixel composer.
43 * - basic AFBC buffer for multiple RGB and YUV pixel formats
44 * - SPARSE layout and SPLIT layout
45 * - 16x16 and 32x8 "wideblk" superblocks
46 * - Tiled header
48 * The ARM AFBC Decoder independent from the VPU Pixel Pipeline, so
50 * into a private internal physical address where the OSD1 Plane pixel
58 static int meson_gxm_afbcd_pixel_fmt(u64 modifier, uint32_t format) in meson_gxm_afbcd_pixel_fmt() argument
60 switch (format) { in meson_gxm_afbcd_pixel_fmt()
66 DRM_DEBUG("unsupported afbc format[%08x]\n", format); in meson_gxm_afbcd_pixel_fmt()
67 return -EINVAL; in meson_gxm_afbcd_pixel_fmt()
71 static bool meson_gxm_afbcd_supported_fmt(u64 modifier, uint32_t format) in meson_gxm_afbcd_supported_fmt() argument
79 return meson_gxm_afbcd_pixel_fmt(modifier, format) >= 0; in meson_gxm_afbcd_supported_fmt()
85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
124 meson_gxm_afbcd_pixel_fmt(priv->afbcd.modifier, in meson_gxm_afbcd_setup()
125 priv->afbcd.format); in meson_gxm_afbcd_setup()
127 if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPARSE) in meson_gxm_afbcd_setup()
130 if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPLIT) in meson_gxm_afbcd_setup()
133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); in meson_gxm_afbcd_setup()
136 priv->viu.osd1_width) | in meson_gxm_afbcd_setup()
138 priv->viu.osd1_height), in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
141 writel_relaxed(priv->viu.osd1_addr >> 4, in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
143 writel_relaxed(priv->viu.osd1_addr >> 4, in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
146 writel_relaxed((0xe4 << 24) | (priv->viu.osd1_addr & 0xffffff), in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
149 if (priv->viu.osd1_width <= 128) in meson_gxm_afbcd_setup()
151 else if (priv->viu.osd1_width <= 256) in meson_gxm_afbcd_setup()
153 else if (priv->viu.osd1_width <= 512) in meson_gxm_afbcd_setup()
155 else if (priv->viu.osd1_width <= 1024) in meson_gxm_afbcd_setup()
157 else if (priv->viu.osd1_width <= 2048) in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
167 priv->viu.osd1_width - 1), in meson_gxm_afbcd_setup()
168 priv->io_base + _REG(OSD1_AFBCD_PIXEL_HSCOPE)); in meson_gxm_afbcd_setup()
172 priv->viu.osd1_height - 1), in meson_gxm_afbcd_setup()
173 priv->io_base + _REG(OSD1_AFBCD_PIXEL_VSCOPE)); in meson_gxm_afbcd_setup()
206 static int meson_g12a_afbcd_pixel_fmt(u64 modifier, uint32_t format) in meson_g12a_afbcd_pixel_fmt() argument
208 switch (format) { in meson_g12a_afbcd_pixel_fmt()
213 return -EINVAL; in meson_g12a_afbcd_pixel_fmt()
221 return -EINVAL; in meson_g12a_afbcd_pixel_fmt()
226 return -EINVAL; in meson_g12a_afbcd_pixel_fmt()
230 DRM_DEBUG("unsupported afbc format[%08x]\n", format); in meson_g12a_afbcd_pixel_fmt()
231 return -EINVAL; in meson_g12a_afbcd_pixel_fmt()
235 static int meson_g12a_afbcd_bpp(uint32_t format) in meson_g12a_afbcd_bpp() argument
237 switch (format) { in meson_g12a_afbcd_bpp()
249 DRM_ERROR("unsupported afbc format[%08x]\n", format); in meson_g12a_afbcd_bpp()
254 static int meson_g12a_afbcd_fmt_to_blk_mode(u64 modifier, uint32_t format) in meson_g12a_afbcd_fmt_to_blk_mode() argument
256 switch (format) { in meson_g12a_afbcd_fmt_to_blk_mode()
268 DRM_DEBUG("unsupported afbc format[%08x]\n", format); in meson_g12a_afbcd_fmt_to_blk_mode()
269 return -EINVAL; in meson_g12a_afbcd_fmt_to_blk_mode()
273 static bool meson_g12a_afbcd_supported_fmt(u64 modifier, uint32_t format) in meson_g12a_afbcd_supported_fmt() argument
275 return meson_g12a_afbcd_pixel_fmt(modifier, format) >= 0; in meson_g12a_afbcd_supported_fmt()
302 priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); in meson_g12a_afbcd_init()
336 priv->io_base + _REG(VPU_MAFBC_SURFACE_CFG)); in meson_g12a_afbcd_disable()
343 u32 format = meson_g12a_afbcd_pixel_fmt(priv->afbcd.modifier, in meson_g12a_afbcd_setup() local
344 priv->afbcd.format); in meson_g12a_afbcd_setup()
346 if (priv->afbcd.modifier & AFBC_FORMAT_MOD_YTR) in meson_g12a_afbcd_setup()
347 format |= VPU_MAFBC_YUV_TRANSFORM; in meson_g12a_afbcd_setup()
349 if (priv->afbcd.modifier & AFBC_FORMAT_MOD_SPLIT) in meson_g12a_afbcd_setup()
350 format |= VPU_MAFBC_BLOCK_SPLIT; in meson_g12a_afbcd_setup()
352 if (priv->afbcd.modifier & AFBC_FORMAT_MOD_TILED) in meson_g12a_afbcd_setup()
353 format |= VPU_MAFBC_TILED_HEADER_EN; in meson_g12a_afbcd_setup()
355 if ((priv->afbcd.modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK) == in meson_g12a_afbcd_setup()
357 format |= FIELD_PREP(VPU_MAFBC_SUPER_BLOCK_ASPECT, 1); in meson_g12a_afbcd_setup()
359 meson_rdma_writel_sync(priv, format, in meson_g12a_afbcd_setup()
362 meson_rdma_writel_sync(priv, priv->viu.osd1_addr, in meson_g12a_afbcd_setup()
367 meson_rdma_writel_sync(priv, priv->viu.osd1_width, in meson_g12a_afbcd_setup()
369 meson_rdma_writel_sync(priv, ALIGN(priv->viu.osd1_height, 32), in meson_g12a_afbcd_setup()
374 meson_rdma_writel_sync(priv, priv->viu.osd1_width - 1, in meson_g12a_afbcd_setup()
378 meson_rdma_writel_sync(priv, priv->viu.osd1_height - 1, in meson_g12a_afbcd_setup()
386 meson_rdma_writel_sync(priv, priv->viu.osd1_width * in meson_g12a_afbcd_setup()
387 (meson_g12a_afbcd_bpp(priv->afbcd.format) / 8), in meson_g12a_afbcd_setup()