drm/meson/meson_dw_mipi_dsi.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 /* Top-level registers */
33  *		1=Enable IP's edpihalt signal to suspend VencL;
35  *     [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36  *		0=Default, use auto-clock gating to save power;
37  *		1=use free-run clock, disable auto-clock gating, for debug mode.
39  *		have auto-clock gating. 1=Enable pixclk.      Default 0.
41  *		have auto-clock gating. 1=Enable sysclk.      Default 0.
50  *		0=16-bit RGB565 config 1;
51  *		1=16-bit RGB565 config 2;
52  *		2=16-bit RGB565 config 3;
53  *		3=18-bit RGB666 config 1;
54  *		4=18-bit RGB666 config 2;
55  *		5=24-bit RGB888;
56  *		6=20-bit YCbCr 4:2:2;
57  *		7=24-bit YCbCr 4:2:2;
58  *		8=16-bit YCbCr 4:2:2;
59  *		9=30-bit RGB;
60  *		10=36-bit RGB;
61  *		11=12-bit YCbCr 4:2:0.
64  *		0=30-bit pixel;
65  *		1=24-bit pixel;
66  *		2=18-bit pixel, RGB666;
67  *		3=16-bit pixel, RGB565.
81  *		If DE input is active low, set to 1 to invert to active high.
83  *		If HS input is active low, set to 1 to invert to active high.
85  *		If VS input is active low, set to 1 to invert to active high.
146  *		For each bit, 1=enable this interrupt, 0=disable.