Lines Matching full:default
12 /* [31: 4] Reserved. Default 0.
13 * [3] RW timing_rst_n: Default 1.
15 * [2] RW dpi_rst_n: Default 1.
17 * [1] RW intr_rst_n: Default 1.
19 * [0] RW dwc_rst_n: Default 1.
29 /* [31: 5] Reserved. Default 0.
30 * [4] RW manual_edpihalt: Default 0.
32 * [3] RW auto_edpihalt_en: Default 0.
35 * [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36 * 0=Default, use auto-clock gating to save power;
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
41 * have auto-clock gating. 1=Enable sysclk. Default 0.
48 /* [31:24] Reserved. Default 0.
49 * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
62 * [19] Reserved. Default 0.
63 * [18:16] RW in_color_mode: Define VENC data width. Default 0.
68 * [15:14] RW chroma_subsample: Define method of chroma subsampling. Default 0.
73 * [13:12] RW comp2_sel: Select which component to be Cr or B: Default 2.
75 * [11:10] RW comp1_sel: Select which component to be Cb or G: Default 1.
77 * [9: 8] RW comp0_sel: Select which component to be Y or R: Default 0.
79 * [7] Reserved. Default 0.
80 * [6] RW de_pol: Default 0.
82 * [5] RW hsync_pol: Default 0.
84 * [4] RW vsync_pol: Default 0.
86 * [3] RW dpicolorm: Signal to IP. Default 0.
87 * [2] RW dpishutdn: Signal to IP. Default 0.
88 * [1] Reserved. Default 0.
89 * [0] Reserved. Default 0.
129 /* [0] R stat_edpihalt: edpihalt signal from IP. Default 0. */
135 /* [31:16] RW intr_stat/clr. Default 0.
145 * [15: 0] RW intr_enable. Default 0.
156 // 31: 2 Reserved. Default 0.
157 // 1: 0 RW mem_pd. Default 3.