drm/meson/meson_dw_hdmi.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12  * Bit 15-10: RW Reserved. Default 1 starting from G12A
33  * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
34  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
35  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
36  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
37  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
38  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
39  * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
40  * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
41  * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
42  * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
43  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
44  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
45  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
46  * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
60  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
108  * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable.
111  * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
112  *     2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
113  * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
140  * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,