Lines Matching full:starting

12  * Bit 15-10: RW Reserved. Default 1 starting from G12A
13  * Bit 9 RW sw_reset_i2c starting from G12A
14  * Bit 8 RW sw_reset_axiarb starting from G12A
15  * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16  * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17  * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
39  * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
40  * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
41  * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
51  * Bit 31:28 RW rxsense_glitch_width: starting from G12A
52  * Bit 27:16 RW rxsense_valid_width: starting from G12A
61  * [  7] rxsense_fall starting from G12A
62  * [  6] rxsense_rise starting from G12A
63  * [  5] err_i2c_timeout starting from G12A
76  * Bit     7 RW rxsense_fall starting from G12A
77  * Bit     6 RW rxsense_rise starting from G12A
78  * Bit     5 RW err_i2c_timeout starting from G12A
86  * [7]    rxsense_fall starting from G12A
87  * [6]    rxsense_rise starting from G12A
88  * [5]    err_i2c_timeout starting from G12A