Lines Matching +full:hdmi +full:- +full:bridge
1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <drm/bridge/dw_hdmi.h>
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
36 * DOC: HDMI Output
38 * HDMI Output is composed of :
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
50 * | Synopsys HDMI | HDMI PHY |=> TMDS
55 * The HDMI TOP block only supports HPD sensing.
56 * The Synopsys HDMI Controller interrupt is routed
59 * HDMI Controller is done a pair of addr+read/write
61 * The HDMI PHY is configured by registers in the
65 * block and the VPU HDMI mux selects either the ENCI
71 * HDMI controller.
74 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
79 * - HPD Rise & Fall interrupt
80 * - HDMI Controller Interrupt
81 * - HDMI PHY Init for 480i to 1080p60
82 * - VENC & HDMI Clock setup for 480i to 1080p60
83 * - VENC Mode setup for 480i to 1080p60
87 * - PHY, Clock and Mode setup for 2k && 4k modes
88 * - SDDC Scrambling mode for HDMI 2.0a
89 * - HDCP Setup
90 * - CEC Management
149 struct dw_hdmi *hdmi; member
150 struct drm_bridge *bridge; member
156 return of_device_is_compatible(dw_hdmi->dev->of_node, compat); in dw_hdmi_is_compatible()
159 /* PHY (via TOP bridge) and Controller dedicated register interface */
170 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
171 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
174 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
175 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
185 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_read()
196 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
197 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
200 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_write()
208 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_write()
217 unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr); in dw_hdmi_top_write_bits()
222 dw_hdmi->data->top_write(dw_hdmi, addr, data); in dw_hdmi_top_write_bits()
234 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
235 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
238 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
239 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
249 return readb(dw_hdmi->hdmitx + addr); in dw_hdmi_g12a_dwc_read()
260 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
261 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
264 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_write()
272 writeb(data, dw_hdmi->hdmitx + addr); in dw_hdmi_g12a_dwc_write()
281 unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr); in dw_hdmi_dwc_write_bits()
286 dw_hdmi->data->dwc_write(dw_hdmi, addr, data); in dw_hdmi_dwc_write_bits()
289 /* Bridge */
296 struct meson_drm *priv = dw_hdmi->priv; in meson_hdmi_phy_setup_mode()
297 unsigned int pixel_clock = mode->clock; in meson_hdmi_phy_setup_mode()
302 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || in meson_hdmi_phy_setup_mode()
303 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
306 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); in meson_hdmi_phy_setup_mode()
307 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); in meson_hdmi_phy_setup_mode()
310 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); in meson_hdmi_phy_setup_mode()
311 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); in meson_hdmi_phy_setup_mode()
314 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); in meson_hdmi_phy_setup_mode()
315 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); in meson_hdmi_phy_setup_mode()
318 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); in meson_hdmi_phy_setup_mode()
319 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); in meson_hdmi_phy_setup_mode()
322 "amlogic,meson-gxbb-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
325 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); in meson_hdmi_phy_setup_mode()
326 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); in meson_hdmi_phy_setup_mode()
329 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283); in meson_hdmi_phy_setup_mode()
330 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b); in meson_hdmi_phy_setup_mode()
333 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122); in meson_hdmi_phy_setup_mode()
334 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b); in meson_hdmi_phy_setup_mode()
337 "amlogic,meson-g12a-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
340 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4); in meson_hdmi_phy_setup_mode()
341 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
342 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b); in meson_hdmi_phy_setup_mode()
345 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262); in meson_hdmi_phy_setup_mode()
346 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
347 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
350 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242); in meson_hdmi_phy_setup_mode()
351 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
352 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
359 struct meson_drm *priv = dw_hdmi->priv; in meson_dw_hdmi_phy_reset()
362 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
367 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
372 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, in dw_hdmi_phy_init() argument
377 bool is_hdmi2_sink = display->hdmi.scdc.supported; in dw_hdmi_phy_init()
378 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_phy_init()
380 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
383 DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name, in dw_hdmi_phy_init()
384 mode->clock > 340000 ? 40 : 10); in dw_hdmi_phy_init()
388 dw_hdmi_bus_fmt_is_420(hdmi)) in dw_hdmi_phy_init()
392 if (mode->clock > 340000 && !mode_is_420) { in dw_hdmi_phy_init()
393 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, in dw_hdmi_phy_init()
395 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, in dw_hdmi_phy_init()
398 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, in dw_hdmi_phy_init()
400 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, in dw_hdmi_phy_init()
405 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); in dw_hdmi_phy_init()
407 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); in dw_hdmi_phy_init()
413 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); in dw_hdmi_phy_init()
415 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); in dw_hdmi_phy_init()
425 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
426 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
428 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
430 /* Temporary Disable HDMI video stream to HDMI-TX */ in dw_hdmi_phy_init()
432 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
434 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
436 /* Re-Enable VENC video stream */ in dw_hdmi_phy_init()
437 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
438 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
440 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
442 /* Push back HDMI clock settings */ in dw_hdmi_phy_init()
444 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
446 /* Enable and Select HDMI video source for HDMI-TX */ in dw_hdmi_phy_init()
447 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
449 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
452 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
457 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, in dw_hdmi_phy_disable() argument
461 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_phy_disable()
466 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init); in dw_hdmi_phy_disable()
467 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init); in dw_hdmi_phy_disable()
470 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi, in dw_hdmi_read_hpd() argument
475 return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ? in dw_hdmi_read_hpd()
479 static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi, in dw_hdmi_setup_hpd() argument
485 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER, in dw_hdmi_setup_hpd()
489 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, in dw_hdmi_setup_hpd()
510 stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT); in dw_hdmi_top_irq()
511 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat); in dw_hdmi_top_irq()
515 dw_hdmi->irq_stat = stat; in dw_hdmi_top_irq()
519 /* HDMI Controller Interrupt */ in dw_hdmi_top_irq()
532 u32 stat = dw_hdmi->irq_stat; in dw_hdmi_top_thread_irq()
541 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected, in dw_hdmi_top_thread_irq()
544 drm_helper_hpd_irq_event(dw_hdmi->bridge->dev); in dw_hdmi_top_thread_irq()
545 drm_bridge_hpd_notify(dw_hdmi->bridge, in dw_hdmi_top_thread_irq()
553 /* DW HDMI Regmap */
560 *result = dw_hdmi->data->dwc_read(dw_hdmi, reg); in meson_dw_hdmi_reg_read()
571 dw_hdmi->data->dwc_write(dw_hdmi, reg, val); in meson_dw_hdmi_reg_write()
614 struct meson_drm *priv = meson_dw_hdmi->priv; in meson_dw_hdmi_init()
617 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
620 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in meson_dw_hdmi_init()
623 reset_control_reset(meson_dw_hdmi->hdmitx_apb); in meson_dw_hdmi_init()
624 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); in meson_dw_hdmi_init()
625 reset_control_reset(meson_dw_hdmi->hdmitx_phy); in meson_dw_hdmi_init()
630 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); in meson_dw_hdmi_init()
632 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); in meson_dw_hdmi_init()
636 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_init()
641 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_init()
645 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); in meson_dw_hdmi_init()
648 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init); in meson_dw_hdmi_init()
649 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init); in meson_dw_hdmi_init()
651 /* Enable HDMI-TX Interrupt */ in meson_dw_hdmi_init()
652 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, in meson_dw_hdmi_init()
655 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, in meson_dw_hdmi_init()
690 struct meson_drm *priv = drm->dev_private; in meson_dw_hdmi_bind()
697 match = of_device_get_match_data(&pdev->dev); in meson_dw_hdmi_bind()
699 dev_err(&pdev->dev, "failed to get match data\n"); in meson_dw_hdmi_bind()
700 return -ENODEV; in meson_dw_hdmi_bind()
706 return -ENOMEM; in meson_dw_hdmi_bind()
708 meson_dw_hdmi->priv = priv; in meson_dw_hdmi_bind()
709 meson_dw_hdmi->dev = dev; in meson_dw_hdmi_bind()
710 meson_dw_hdmi->data = match; in meson_dw_hdmi_bind()
711 dw_plat_data = &meson_dw_hdmi->dw_plat_data; in meson_dw_hdmi_bind()
713 ret = devm_regulator_get_enable_optional(dev, "hdmi"); in meson_dw_hdmi_bind()
714 if (ret < 0 && ret != -ENODEV) in meson_dw_hdmi_bind()
717 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
719 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { in meson_dw_hdmi_bind()
721 return PTR_ERR(meson_dw_hdmi->hdmitx_apb); in meson_dw_hdmi_bind()
724 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
726 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { in meson_dw_hdmi_bind()
728 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); in meson_dw_hdmi_bind()
731 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
733 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { in meson_dw_hdmi_bind()
735 return PTR_ERR(meson_dw_hdmi->hdmitx_phy); in meson_dw_hdmi_bind()
738 meson_dw_hdmi->hdmitx = devm_platform_ioremap_resource(pdev, 0); in meson_dw_hdmi_bind()
739 if (IS_ERR(meson_dw_hdmi->hdmitx)) in meson_dw_hdmi_bind()
740 return PTR_ERR(meson_dw_hdmi->hdmitx); in meson_dw_hdmi_bind()
754 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, in meson_dw_hdmi_bind()
756 if (IS_ERR(dw_plat_data->regm)) in meson_dw_hdmi_bind()
757 return PTR_ERR(dw_plat_data->regm); in meson_dw_hdmi_bind()
767 dev_err(dev, "Failed to request hdmi top irq\n"); in meson_dw_hdmi_bind()
773 /* Bridge / Connector */ in meson_dw_hdmi_bind()
775 dw_plat_data->priv_data = meson_dw_hdmi; in meson_dw_hdmi_bind()
776 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; in meson_dw_hdmi_bind()
777 dw_plat_data->phy_name = "meson_dw_hdmi_phy"; in meson_dw_hdmi_bind()
778 dw_plat_data->phy_data = meson_dw_hdmi; in meson_dw_hdmi_bind()
779 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; in meson_dw_hdmi_bind()
780 dw_plat_data->ycbcr_420_allowed = true; in meson_dw_hdmi_bind()
781 dw_plat_data->disable_cec = true; in meson_dw_hdmi_bind()
782 dw_plat_data->output_port = 1; in meson_dw_hdmi_bind()
784 if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || in meson_dw_hdmi_bind()
785 dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || in meson_dw_hdmi_bind()
786 dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) in meson_dw_hdmi_bind()
787 dw_plat_data->use_drm_infoframe = true; in meson_dw_hdmi_bind()
791 meson_dw_hdmi->hdmi = dw_hdmi_probe(pdev, &meson_dw_hdmi->dw_plat_data); in meson_dw_hdmi_bind()
792 if (IS_ERR(meson_dw_hdmi->hdmi)) in meson_dw_hdmi_bind()
793 return PTR_ERR(meson_dw_hdmi->hdmi); in meson_dw_hdmi_bind()
795 meson_dw_hdmi->bridge = of_drm_find_bridge(pdev->dev.of_node); in meson_dw_hdmi_bind()
797 DRM_DEBUG_DRIVER("HDMI controller initialized\n"); in meson_dw_hdmi_bind()
807 dw_hdmi_unbind(meson_dw_hdmi->hdmi); in meson_dw_hdmi_unbind()
823 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_pm_suspend()
838 dw_hdmi_resume(meson_dw_hdmi->hdmi); in meson_dw_hdmi_pm_resume()
845 return component_add(&pdev->dev, &meson_dw_hdmi_ops); in meson_dw_hdmi_probe()
850 component_del(&pdev->dev, &meson_dw_hdmi_ops); in meson_dw_hdmi_remove()
859 { .compatible = "amlogic,meson-gxbb-dw-hdmi",
861 { .compatible = "amlogic,meson-gxl-dw-hdmi",
863 { .compatible = "amlogic,meson-gxm-dw-hdmi",
865 { .compatible = "amlogic,meson-g12a-dw-hdmi",