Lines Matching refs:priv
37 struct meson_drm *priv; member
38 void (*enable_osd1)(struct meson_drm *priv);
39 void (*enable_vd1)(struct meson_drm *priv);
40 void (*enable_osd1_afbc)(struct meson_drm *priv);
41 void (*disable_osd1_afbc)(struct meson_drm *priv);
53 struct meson_drm *priv = meson_crtc->priv; in meson_crtc_enable_vblank() local
56 meson_venc_enable_vsync(priv); in meson_crtc_enable_vblank()
64 struct meson_drm *priv = meson_crtc->priv; in meson_crtc_disable_vblank() local
68 meson_venc_disable_vsync(priv); in meson_crtc_disable_vblank()
89 struct meson_drm *priv = meson_crtc->priv; in meson_g12a_crtc_atomic_enable() local
100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
125 struct meson_drm *priv = meson_crtc->priv; in meson_crtc_atomic_enable() local
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
152 struct meson_drm *priv = meson_crtc->priv; in meson_g12a_crtc_atomic_disable() local
158 priv->viu.osd1_enabled = false; in meson_g12a_crtc_atomic_disable()
159 priv->viu.osd1_commit = false; in meson_g12a_crtc_atomic_disable()
161 priv->viu.vd1_enabled = false; in meson_g12a_crtc_atomic_disable()
162 priv->viu.vd1_commit = false; in meson_g12a_crtc_atomic_disable()
177 struct meson_drm *priv = meson_crtc->priv; in meson_crtc_atomic_disable() local
183 priv->viu.osd1_enabled = false; in meson_crtc_atomic_disable()
184 priv->viu.osd1_commit = false; in meson_crtc_atomic_disable()
186 priv->viu.vd1_enabled = false; in meson_crtc_atomic_disable()
187 priv->viu.vd1_commit = false; in meson_crtc_atomic_disable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
223 struct meson_drm *priv = meson_crtc->priv; in meson_crtc_atomic_flush() local
225 priv->viu.osd1_commit = true; in meson_crtc_atomic_flush()
226 priv->viu.vd1_commit = true; in meson_crtc_atomic_flush()
243 static void meson_crtc_enable_osd1(struct meson_drm *priv) in meson_crtc_enable_osd1() argument
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
249 static void meson_crtc_g12a_enable_osd1_afbc(struct meson_drm *priv) in meson_crtc_g12a_enable_osd1_afbc() argument
251 writel_relaxed(priv->viu.osd1_blk2_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
252 priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4)); in meson_crtc_g12a_enable_osd1_afbc()
255 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_crtc_g12a_enable_osd1_afbc()
257 writel_relaxed(priv->viu.osd1_blk1_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
258 priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4)); in meson_crtc_g12a_enable_osd1_afbc()
260 meson_viu_g12a_enable_osd1_afbc(priv); in meson_crtc_g12a_enable_osd1_afbc()
263 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_crtc_g12a_enable_osd1_afbc()
266 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); in meson_crtc_g12a_enable_osd1_afbc()
269 static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv) in meson_g12a_crtc_enable_osd1() argument
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h, in meson_g12a_crtc_enable_osd1()
272 priv->io_base + in meson_g12a_crtc_enable_osd1()
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v, in meson_g12a_crtc_enable_osd1()
275 priv->io_base + in meson_g12a_crtc_enable_osd1()
277 writel_relaxed(priv->viu.osb_blend0_size, in meson_g12a_crtc_enable_osd1()
278 priv->io_base + in meson_g12a_crtc_enable_osd1()
280 writel_relaxed(priv->viu.osb_blend1_size, in meson_g12a_crtc_enable_osd1()
281 priv->io_base + in meson_g12a_crtc_enable_osd1()
284 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_g12a_crtc_enable_osd1()
287 static void meson_crtc_enable_vd1(struct meson_drm *priv) in meson_crtc_enable_vd1() argument
293 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_vd1()
296 priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0, in meson_crtc_enable_vd1()
297 priv->io_base + _REG(VIU_MISC_CTRL0)); in meson_crtc_enable_vd1()
300 static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) in meson_g12a_crtc_enable_vd1() argument
306 priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_g12a_crtc_enable_vd1()
308 writel_relaxed(priv->viu.vd1_afbc ? in meson_g12a_crtc_enable_vd1()
310 priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL)); in meson_g12a_crtc_enable_vd1()
313 void meson_crtc_irq(struct meson_drm *priv) in meson_crtc_irq() argument
315 struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc); in meson_crtc_irq()
319 if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { in meson_crtc_irq()
320 writel_relaxed(priv->viu.osd1_ctrl_stat, in meson_crtc_irq()
321 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_crtc_irq()
322 writel_relaxed(priv->viu.osd1_ctrl_stat2, in meson_crtc_irq()
323 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_crtc_irq()
324 writel_relaxed(priv->viu.osd1_blk0_cfg[0], in meson_crtc_irq()
325 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); in meson_crtc_irq()
326 writel_relaxed(priv->viu.osd1_blk0_cfg[1], in meson_crtc_irq()
327 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1)); in meson_crtc_irq()
328 writel_relaxed(priv->viu.osd1_blk0_cfg[2], in meson_crtc_irq()
329 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2)); in meson_crtc_irq()
330 writel_relaxed(priv->viu.osd1_blk0_cfg[3], in meson_crtc_irq()
331 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); in meson_crtc_irq()
332 writel_relaxed(priv->viu.osd1_blk0_cfg[4], in meson_crtc_irq()
333 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); in meson_crtc_irq()
335 if (priv->viu.osd1_afbcd) { in meson_crtc_irq()
337 meson_crtc->enable_osd1_afbc(priv); in meson_crtc_irq()
340 meson_crtc->disable_osd1_afbc(priv); in meson_crtc_irq()
341 if (priv->afbcd.ops) { in meson_crtc_irq()
342 priv->afbcd.ops->reset(priv); in meson_crtc_irq()
343 priv->afbcd.ops->disable(priv); in meson_crtc_irq()
348 writel_relaxed(priv->viu.osd_sc_ctrl0, in meson_crtc_irq()
349 priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_crtc_irq()
350 writel_relaxed(priv->viu.osd_sc_i_wh_m1, in meson_crtc_irq()
351 priv->io_base + _REG(VPP_OSD_SCI_WH_M1)); in meson_crtc_irq()
352 writel_relaxed(priv->viu.osd_sc_o_h_start_end, in meson_crtc_irq()
353 priv->io_base + _REG(VPP_OSD_SCO_H_START_END)); in meson_crtc_irq()
354 writel_relaxed(priv->viu.osd_sc_o_v_start_end, in meson_crtc_irq()
355 priv->io_base + _REG(VPP_OSD_SCO_V_START_END)); in meson_crtc_irq()
356 writel_relaxed(priv->viu.osd_sc_v_ini_phase, in meson_crtc_irq()
357 priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE)); in meson_crtc_irq()
358 writel_relaxed(priv->viu.osd_sc_v_phase_step, in meson_crtc_irq()
359 priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP)); in meson_crtc_irq()
360 writel_relaxed(priv->viu.osd_sc_h_ini_phase, in meson_crtc_irq()
361 priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE)); in meson_crtc_irq()
362 writel_relaxed(priv->viu.osd_sc_h_phase_step, in meson_crtc_irq()
363 priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP)); in meson_crtc_irq()
364 writel_relaxed(priv->viu.osd_sc_h_ctrl0, in meson_crtc_irq()
365 priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_crtc_irq()
366 writel_relaxed(priv->viu.osd_sc_v_ctrl0, in meson_crtc_irq()
367 priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_crtc_irq()
369 if (!priv->viu.osd1_afbcd) in meson_crtc_irq()
370 meson_canvas_config(priv->canvas, priv->canvas_id_osd1, in meson_crtc_irq()
371 priv->viu.osd1_addr, in meson_crtc_irq()
372 priv->viu.osd1_stride, in meson_crtc_irq()
373 priv->viu.osd1_height, in meson_crtc_irq()
379 meson_crtc->enable_osd1(priv); in meson_crtc_irq()
381 if (priv->viu.osd1_afbcd) { in meson_crtc_irq()
382 priv->afbcd.ops->reset(priv); in meson_crtc_irq()
383 priv->afbcd.ops->setup(priv); in meson_crtc_irq()
384 priv->afbcd.ops->enable(priv); in meson_crtc_irq()
388 priv->viu.osd1_commit = false; in meson_crtc_irq()
392 if (priv->viu.vd1_enabled && priv->viu.vd1_commit) { in meson_crtc_irq()
394 if (priv->viu.vd1_afbc) { in meson_crtc_irq()
395 writel_relaxed(priv->viu.vd1_afbc_head_addr, in meson_crtc_irq()
396 priv->io_base + in meson_crtc_irq()
398 writel_relaxed(priv->viu.vd1_afbc_body_addr, in meson_crtc_irq()
399 priv->io_base + in meson_crtc_irq()
401 writel_relaxed(priv->viu.vd1_afbc_en, in meson_crtc_irq()
402 priv->io_base + in meson_crtc_irq()
404 writel_relaxed(priv->viu.vd1_afbc_mode, in meson_crtc_irq()
405 priv->io_base + in meson_crtc_irq()
407 writel_relaxed(priv->viu.vd1_afbc_size_in, in meson_crtc_irq()
408 priv->io_base + in meson_crtc_irq()
410 writel_relaxed(priv->viu.vd1_afbc_dec_def_color, in meson_crtc_irq()
411 priv->io_base + in meson_crtc_irq()
413 writel_relaxed(priv->viu.vd1_afbc_conv_ctrl, in meson_crtc_irq()
414 priv->io_base + in meson_crtc_irq()
416 writel_relaxed(priv->viu.vd1_afbc_size_out, in meson_crtc_irq()
417 priv->io_base + in meson_crtc_irq()
419 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl, in meson_crtc_irq()
420 priv->io_base + in meson_crtc_irq()
422 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w, in meson_crtc_irq()
423 priv->io_base + in meson_crtc_irq()
425 writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope, in meson_crtc_irq()
426 priv->io_base + in meson_crtc_irq()
428 writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope, in meson_crtc_irq()
429 priv->io_base + in meson_crtc_irq()
431 writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope, in meson_crtc_irq()
432 priv->io_base+ in meson_crtc_irq()
434 writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope, in meson_crtc_irq()
435 priv->io_base + in meson_crtc_irq()
437 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h, in meson_crtc_irq()
438 priv->io_base + in meson_crtc_irq()
441 switch (priv->viu.vd1_planes) { in meson_crtc_irq()
443 meson_canvas_config(priv->canvas, in meson_crtc_irq()
444 priv->canvas_id_vd1_2, in meson_crtc_irq()
445 priv->viu.vd1_addr2, in meson_crtc_irq()
446 priv->viu.vd1_stride2, in meson_crtc_irq()
447 priv->viu.vd1_height2, in meson_crtc_irq()
453 meson_canvas_config(priv->canvas, in meson_crtc_irq()
454 priv->canvas_id_vd1_1, in meson_crtc_irq()
455 priv->viu.vd1_addr1, in meson_crtc_irq()
456 priv->viu.vd1_stride1, in meson_crtc_irq()
457 priv->viu.vd1_height1, in meson_crtc_irq()
463 meson_canvas_config(priv->canvas, in meson_crtc_irq()
464 priv->canvas_id_vd1_0, in meson_crtc_irq()
465 priv->viu.vd1_addr0, in meson_crtc_irq()
466 priv->viu.vd1_stride0, in meson_crtc_irq()
467 priv->viu.vd1_height0, in meson_crtc_irq()
473 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); in meson_crtc_irq()
476 writel_relaxed(priv->viu.vd1_if0_gen_reg, in meson_crtc_irq()
477 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
479 writel_relaxed(priv->viu.vd1_if0_gen_reg, in meson_crtc_irq()
480 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
482 writel_relaxed(priv->viu.vd1_if0_gen_reg2, in meson_crtc_irq()
483 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
485 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, in meson_crtc_irq()
486 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
488 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl, in meson_crtc_irq()
489 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
491 writel_relaxed(priv->viu.viu_vd1_fmt_w, in meson_crtc_irq()
492 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
494 writel_relaxed(priv->viu.viu_vd1_fmt_w, in meson_crtc_irq()
495 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
497 writel_relaxed(priv->viu.vd1_if0_canvas0, in meson_crtc_irq()
498 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
500 writel_relaxed(priv->viu.vd1_if0_canvas0, in meson_crtc_irq()
501 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
503 writel_relaxed(priv->viu.vd1_if0_canvas0, in meson_crtc_irq()
504 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
506 writel_relaxed(priv->viu.vd1_if0_canvas0, in meson_crtc_irq()
507 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
509 writel_relaxed(priv->viu.vd1_if0_luma_x0, in meson_crtc_irq()
510 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
512 writel_relaxed(priv->viu.vd1_if0_luma_x0, in meson_crtc_irq()
513 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
515 writel_relaxed(priv->viu.vd1_if0_luma_x0, in meson_crtc_irq()
516 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
518 writel_relaxed(priv->viu.vd1_if0_luma_x0, in meson_crtc_irq()
519 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
521 writel_relaxed(priv->viu.vd1_if0_luma_y0, in meson_crtc_irq()
522 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
524 writel_relaxed(priv->viu.vd1_if0_luma_y0, in meson_crtc_irq()
525 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
527 writel_relaxed(priv->viu.vd1_if0_luma_y0, in meson_crtc_irq()
528 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
530 writel_relaxed(priv->viu.vd1_if0_luma_y0, in meson_crtc_irq()
531 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
533 writel_relaxed(priv->viu.vd1_if0_chroma_x0, in meson_crtc_irq()
534 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
536 writel_relaxed(priv->viu.vd1_if0_chroma_x0, in meson_crtc_irq()
537 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
539 writel_relaxed(priv->viu.vd1_if0_chroma_x0, in meson_crtc_irq()
540 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
542 writel_relaxed(priv->viu.vd1_if0_chroma_x0, in meson_crtc_irq()
543 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
545 writel_relaxed(priv->viu.vd1_if0_chroma_y0, in meson_crtc_irq()
546 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
548 writel_relaxed(priv->viu.vd1_if0_chroma_y0, in meson_crtc_irq()
549 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
551 writel_relaxed(priv->viu.vd1_if0_chroma_y0, in meson_crtc_irq()
552 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
554 writel_relaxed(priv->viu.vd1_if0_chroma_y0, in meson_crtc_irq()
555 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
557 writel_relaxed(priv->viu.vd1_if0_repeat_loop, in meson_crtc_irq()
558 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
560 writel_relaxed(priv->viu.vd1_if0_repeat_loop, in meson_crtc_irq()
561 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
563 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat, in meson_crtc_irq()
564 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
566 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat, in meson_crtc_irq()
567 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
569 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat, in meson_crtc_irq()
570 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
572 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat, in meson_crtc_irq()
573 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
575 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat, in meson_crtc_irq()
576 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
578 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat, in meson_crtc_irq()
579 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
581 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat, in meson_crtc_irq()
582 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
584 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat, in meson_crtc_irq()
585 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
587 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
589 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
591 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
593 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
595 writel_relaxed(priv->viu.vd1_range_map_y, in meson_crtc_irq()
596 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
598 writel_relaxed(priv->viu.vd1_range_map_cb, in meson_crtc_irq()
599 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
601 writel_relaxed(priv->viu.vd1_range_map_cr, in meson_crtc_irq()
602 priv->io_base + meson_crtc->viu_offset + in meson_crtc_irq()
610 priv->io_base + _REG(VPP_SC_MISC)); in meson_crtc_irq()
611 writel_relaxed(priv->viu.vpp_pic_in_height, in meson_crtc_irq()
612 priv->io_base + _REG(VPP_PIC_IN_HEIGHT)); in meson_crtc_irq()
613 writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end, in meson_crtc_irq()
614 priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END)); in meson_crtc_irq()
615 writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end, in meson_crtc_irq()
616 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); in meson_crtc_irq()
617 writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end, in meson_crtc_irq()
618 priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END)); in meson_crtc_irq()
619 writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end, in meson_crtc_irq()
620 priv->io_base + _REG(VPP_BLEND_VD2_V_START_END)); in meson_crtc_irq()
621 writel_relaxed(priv->viu.vpp_hsc_region12_startp, in meson_crtc_irq()
622 priv->io_base + _REG(VPP_HSC_REGION12_STARTP)); in meson_crtc_irq()
623 writel_relaxed(priv->viu.vpp_hsc_region34_startp, in meson_crtc_irq()
624 priv->io_base + _REG(VPP_HSC_REGION34_STARTP)); in meson_crtc_irq()
625 writel_relaxed(priv->viu.vpp_hsc_region4_endp, in meson_crtc_irq()
626 priv->io_base + _REG(VPP_HSC_REGION4_ENDP)); in meson_crtc_irq()
627 writel_relaxed(priv->viu.vpp_hsc_start_phase_step, in meson_crtc_irq()
628 priv->io_base + _REG(VPP_HSC_START_PHASE_STEP)); in meson_crtc_irq()
629 writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope, in meson_crtc_irq()
630 priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE)); in meson_crtc_irq()
631 writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope, in meson_crtc_irq()
632 priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE)); in meson_crtc_irq()
633 writel_relaxed(priv->viu.vpp_line_in_length, in meson_crtc_irq()
634 priv->io_base + _REG(VPP_LINE_IN_LENGTH)); in meson_crtc_irq()
635 writel_relaxed(priv->viu.vpp_preblend_h_size, in meson_crtc_irq()
636 priv->io_base + _REG(VPP_PREBLEND_H_SIZE)); in meson_crtc_irq()
637 writel_relaxed(priv->viu.vpp_vsc_region12_startp, in meson_crtc_irq()
638 priv->io_base + _REG(VPP_VSC_REGION12_STARTP)); in meson_crtc_irq()
639 writel_relaxed(priv->viu.vpp_vsc_region34_startp, in meson_crtc_irq()
640 priv->io_base + _REG(VPP_VSC_REGION34_STARTP)); in meson_crtc_irq()
641 writel_relaxed(priv->viu.vpp_vsc_region4_endp, in meson_crtc_irq()
642 priv->io_base + _REG(VPP_VSC_REGION4_ENDP)); in meson_crtc_irq()
643 writel_relaxed(priv->viu.vpp_vsc_start_phase_step, in meson_crtc_irq()
644 priv->io_base + _REG(VPP_VSC_START_PHASE_STEP)); in meson_crtc_irq()
645 writel_relaxed(priv->viu.vpp_vsc_ini_phase, in meson_crtc_irq()
646 priv->io_base + _REG(VPP_VSC_INI_PHASE)); in meson_crtc_irq()
647 writel_relaxed(priv->viu.vpp_vsc_phase_ctrl, in meson_crtc_irq()
648 priv->io_base + _REG(VPP_VSC_PHASE_CTRL)); in meson_crtc_irq()
649 writel_relaxed(priv->viu.vpp_hsc_phase_ctrl, in meson_crtc_irq()
650 priv->io_base + _REG(VPP_HSC_PHASE_CTRL)); in meson_crtc_irq()
651 writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_crtc_irq()
655 meson_crtc->enable_vd1(priv); in meson_crtc_irq()
657 priv->viu.vd1_commit = false; in meson_crtc_irq()
663 drm_crtc_handle_vblank(priv->crtc); in meson_crtc_irq()
665 spin_lock_irqsave(&priv->drm->event_lock, flags); in meson_crtc_irq()
667 drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event); in meson_crtc_irq()
668 drm_crtc_vblank_put(priv->crtc); in meson_crtc_irq()
671 spin_unlock_irqrestore(&priv->drm->event_lock, flags); in meson_crtc_irq()
674 int meson_crtc_create(struct meson_drm *priv) in meson_crtc_create() argument
680 meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc), in meson_crtc_create()
685 meson_crtc->priv = priv; in meson_crtc_create()
687 ret = drm_crtc_init_with_planes(priv->drm, crtc, in meson_crtc_create()
688 priv->primary_plane, NULL, in meson_crtc_create()
691 dev_err(priv->drm->dev, "Failed to init CRTC\n"); in meson_crtc_create()
695 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { in meson_crtc_create()
707 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { in meson_crtc_create()
716 priv->crtc = crtc; in meson_crtc_create()