Lines Matching +full:0 +full:x25c
9 #define GRL_INT_MASK 0x18
10 #define GRL_IFM_PORT 0x188
11 #define GRL_CH_SWAP 0x198
12 #define LR_SWAP BIT(0)
17 #define GRL_I2S_C_STA0 0x140
18 #define GRL_I2S_C_STA1 0x144
19 #define GRL_I2S_C_STA2 0x148
20 #define GRL_I2S_C_STA3 0x14C
21 #define GRL_I2S_C_STA4 0x150
22 #define GRL_I2S_UV 0x154
23 #define I2S_UV_V BIT(0)
25 #define I2S_UV_CH_EN_MASK 0x3c
29 #define GRL_ACP_ISRC_CTRL 0x158
30 #define VS_EN BIT(0)
35 #define GRL_CTS_CTRL 0x160
36 #define CTS_CTRL_SOFT BIT(0)
37 #define GRL_INT 0x14
38 #define INT_MDI BIT(0)
46 #define GRL_INT_MASK 0x18
47 #define GRL_CTRL 0x1C
54 #define GRL_STATUS 0x20
55 #define STATUS_HTPLG BIT(0)
57 #define GRL_DIVN 0x170
59 #define GRL_AUDIO_CFG 0x17C
60 #define AUDIO_ZERO BIT(0)
68 #define GRL_NCTS 0x184
69 #define GRL_CH_SW0 0x18C
70 #define GRL_CH_SW1 0x190
71 #define GRL_CH_SW2 0x194
73 #define GRL_INFOFRM_VER 0x19C
74 #define GRL_INFOFRM_TYPE 0x1A0
75 #define GRL_INFOFRM_LNG 0x1A4
76 #define GRL_MIX_CTRL 0x1B4
77 #define MIX_CTRL_SRC_EN BIT(0)
80 #define GRL_AOUT_CFG 0x1C4
81 #define AOUT_BNUM_SEL_MASK 0x03
82 #define AOUT_24BIT 0x00
83 #define AOUT_20BIT 0x02
84 #define AOUT_16BIT 0x03
89 #define GRL_SHIFT_L1 0x1C0
90 #define GRL_SHIFT_R2 0x1B0
92 #define GRL_CFG0 0x24
93 #define CFG0_I2S_MODE_MASK 0x3
94 #define CFG0_I2S_MODE_RTJ 0x1
95 #define CFG0_I2S_MODE_LTJ 0x0
96 #define CFG0_I2S_MODE_I2S 0x2
97 #define CFG0_W_LENGTH_MASK 0x30
98 #define CFG0_W_LENGTH_24BIT 0x00
99 #define CFG0_W_LENGTH_16BIT 0x10
100 #define GRL_CFG1 0x28
101 #define CFG1_EDG_SEL BIT(0)
105 #define GRL_CFG2 0x2c
111 #define GRL_CFG3 0x30
112 #define CFG3_AES_KEY_INDEX_MASK 0x3f
115 #define GRL_CFG4 0x34
120 #define GRL_CFG5 0x38
121 #define CFG5_CD_RATIO_MASK 0x8F
122 #define CFG5_FS128 (0x1 << 4)
123 #define CFG5_FS256 (0x2 << 4)
124 #define CFG5_FS384 (0x3 << 4)
125 #define CFG5_FS512 (0x4 << 4)
126 #define CFG5_FS768 (0x6 << 4)
127 #define DUMMY_304 0x304
128 #define CHMO_SEL (0x3 << 2)
129 #define CHM1_SEL (0x3 << 4)
130 #define CHM2_SEL (0x3 << 6)
133 #define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
134 #define NEW_GCP_CTRL BIT(0)
135 #define NEW_GCP_CTRL_MERGE BIT(0)
136 #define GRL_L_STATUS_0 0x200
137 #define GRL_L_STATUS_1 0x204
138 #define GRL_L_STATUS_2 0x208
139 #define GRL_L_STATUS_3 0x20c
140 #define GRL_L_STATUS_4 0x210
141 #define GRL_L_STATUS_5 0x214
142 #define GRL_L_STATUS_6 0x218
143 #define GRL_L_STATUS_7 0x21c
144 #define GRL_L_STATUS_8 0x220
145 #define GRL_L_STATUS_9 0x224
146 #define GRL_L_STATUS_10 0x228
147 #define GRL_L_STATUS_11 0x22c
148 #define GRL_L_STATUS_12 0x230
149 #define GRL_L_STATUS_13 0x234
150 #define GRL_L_STATUS_14 0x238
151 #define GRL_L_STATUS_15 0x23c
152 #define GRL_L_STATUS_16 0x240
153 #define GRL_L_STATUS_17 0x244
154 #define GRL_L_STATUS_18 0x248
155 #define GRL_L_STATUS_19 0x24c
156 #define GRL_L_STATUS_20 0x250
157 #define GRL_L_STATUS_21 0x254
158 #define GRL_L_STATUS_22 0x258
159 #define GRL_L_STATUS_23 0x25c
160 #define GRL_R_STATUS_0 0x260
161 #define GRL_R_STATUS_1 0x264
162 #define GRL_R_STATUS_2 0x268
163 #define GRL_R_STATUS_3 0x26c
164 #define GRL_R_STATUS_4 0x270
165 #define GRL_R_STATUS_5 0x274
166 #define GRL_R_STATUS_6 0x278
167 #define GRL_R_STATUS_7 0x27c
168 #define GRL_R_STATUS_8 0x280
169 #define GRL_R_STATUS_9 0x284
170 #define GRL_R_STATUS_10 0x288
171 #define GRL_R_STATUS_11 0x28c
172 #define GRL_R_STATUS_12 0x290
173 #define GRL_R_STATUS_13 0x294
174 #define GRL_R_STATUS_14 0x298
175 #define GRL_R_STATUS_15 0x29c
176 #define GRL_R_STATUS_16 0x2a0
177 #define GRL_R_STATUS_17 0x2a4
178 #define GRL_R_STATUS_18 0x2a8
179 #define GRL_R_STATUS_19 0x2ac
180 #define GRL_R_STATUS_20 0x2b0
181 #define GRL_R_STATUS_21 0x2b4
182 #define GRL_R_STATUS_22 0x2b8
183 #define GRL_R_STATUS_23 0x2bc
184 #define GRL_ABIST_CTRL0 0x2D4
185 #define GRL_ABIST_CTRL1 0x2D8
187 #define ABIST_DATA_FMT (0x7 << 0)
188 #define VIDEO_CFG_0 0x380
189 #define VIDEO_CFG_1 0x384
190 #define VIDEO_CFG_2 0x388
191 #define VIDEO_CFG_3 0x38c
192 #define VIDEO_CFG_4 0x390
195 #define GEN_RGB (0 << 7)
197 #define HDMI_SYS_CFG1C 0x000
198 #define HDMI_ON BIT(0)
203 #define SYS_KEYMASK1 (0xff << 8)
204 #define SYS_KEYMASK2 (0xff << 16)
213 #define HDMI_SYS_CFG20 0x004
215 #define COLOR_8BIT_MODE (0 << 1)
219 #define DEEP_COLOR_EN BIT(0)
229 #define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001