Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
26 #define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
27 #define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)
28 #define DA_CKM_XTAL_CK_FORCE_EN BIT(8)
29 #define DA_CKM_BIAS_LPF_EN_FORCE_VAL BIT(7)
30 #define DA_CKM_BIAS_LPF_EN_FORCE_EN BIT(6)
31 #define DA_CKM_BIAS_EN_FORCE_VAL BIT(5)
32 #define DA_CKM_BIAS_EN_FORCE_EN BIT(4)
33 #define DA_XTP_GLB_AVD10_ON_FORCE_VAL BIT(3)
34 #define DA_XTP_GLB_AVD10_ON_FORCE BIT(2)
35 #define DA_XTP_GLB_LDO_EN_FORCE_VAL BIT(1)
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
50 #define RG_DPAUX_RX_VALID_DEGLITCH_EN BIT(2)
51 #define RG_XTP_GLB_CKDET_EN BIT(1)
52 #define RG_DPAUX_RX_EN BIT(0)
57 #define DP_PWR_STATE_BANDGAP BIT(0)
58 #define DP_PWR_STATE_BANDGAP_TPLL BIT(1)
65 #define DP_TX1_VOLT_SWING_MASK GENMASK(9, 8)
66 #define DP_TX1_VOLT_SWING_SHIFT 8
73 #define SW_RST_B_PHYD BIT(4)
75 #define IRQ_MASK_AUX_TOP_IRQ BIT(2)
77 #define MEM_ISO_EN BIT(0)
78 #define FUSE_SEL BIT(2)
83 #define VIDEO_MUTE_SW_DP_ENC0_P0 BIT(2)
84 #define VIDEO_MUTE_SEL_DP_ENC0_P0 BIT(3)
85 #define ENHANCED_FRAME_EN_DP_ENC0_P0 BIT(4)
87 #define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8)
88 #define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9)
103 #define HSP_SW_DP_ENC0_P0_MASK BIT(15)
106 #define VSP_SW_DP_ENC0_P0_MASK BIT(15)
108 #define HTOTAL_SEL_DP_ENC0_P0 BIT(0)
109 #define VTOTAL_SEL_DP_ENC0_P0 BIT(1)
110 #define HSTART_SEL_DP_ENC0_P0 BIT(2)
111 #define VSTART_SEL_DP_ENC0_P0 BIT(3)
112 #define HWIDTH_SEL_DP_ENC0_P0 BIT(4)
113 #define VHEIGHT_SEL_DP_ENC0_P0 BIT(5)
114 #define HSP_SEL_DP_ENC0_P0 BIT(6)
115 #define HSW_SEL_DP_ENC0_P0 BIT(7)
116 #define VSP_SEL_DP_ENC0_P0 BIT(8)
117 #define VSW_SEL_DP_ENC0_P0 BIT(9)
118 #define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 BIT(11)
119 #define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0 BIT(12)
122 #define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK BIT(11)
125 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8)
126 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)
127 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << 8)
128 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT (2 << 8)
129 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << 8)
130 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << 8)
135 #define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)
140 #define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK BIT(2)
141 #define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK BIT(8)
145 #define AU_EN_DP_ENC0_P0 BIT(6)
146 #define AUDIO_8CH_EN_DP_ENC0_P0_MASK BIT(7)
147 #define AUDIO_8CH_SEL_DP_ENC0_P0_MASK BIT(8)
148 #define AUDIO_2CH_EN_DP_ENC0_P0_MASK BIT(14)
149 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)
160 #define ISRC_CONT_DP_ENC0_P0 BIT(0)
161 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)
162 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
163 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
164 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)
165 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8)
166 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8)
167 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)
168 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
169 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
170 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8)
171 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8)
172 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8)
173 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)
177 #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
202 #define AUDIO_CH_SRC_SEL_DP_ENC0_P0 BIT(4)
203 #define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
209 #define SDP_PACKET_W_DP_ENC1_P0 BIT(5)
210 #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5)
213 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
215 #define AU_PRTY_REGEN_DP_ENC1_P0_MASK BIT(8)
216 #define AU_CH_STS_REGEN_DP_ENC1_P0_MASK BIT(9)
217 #define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK BIT(12)
219 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8)
227 #define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0)
228 #define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 BIT(4)
229 #define SDP_DP13_EN_DP_ENC1_P0 BIT(8)
230 #define BS2BS_MODE_DP_ENC1_P0 BIT(12)
239 #define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12)
243 #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
244 #define DP_ENC_DUMMY_RW_1 BIT(9)
248 #define PATTERN1_EN_DP_TRANS_P0_MASK BIT(12)
249 #define PATTERN2_EN_DP_TRANS_P0_MASK BIT(13)
250 #define PATTERN3_EN_DP_TRANS_P0_MASK BIT(14)
251 #define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)
253 #define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0)
255 #define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0 BIT(13)
261 #define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8)
264 #define HPD_DB_DP_TRANS_P0_MASK BIT(2)
268 #define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << 4)
269 #define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << 4)
270 #define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << 4)
273 #define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6))
277 #define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)
281 #define FEC_EN_DP_TRANS_P0_MASK BIT(0)
282 #define FEC_CLOCK_EN_MODE_DP_TRANS_P0 BIT(3)
284 #define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK BIT(8)
285 #define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK BIT(9)
286 #define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK BIT(10)
287 #define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK BIT(11)
294 #define DP_TRANS_DUMMY_RW_0 BIT(3)
305 #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
308 #define AUX_RD_MODE_AUX_TX_P0_MASK BIT(9)
309 #define AUX_RX_FIFO_READ_PULSE_TX_P0 BIT(8)
315 #define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0)
317 #define AUX_NO_LENGTH_AUX_TX_P0 BIT(0)
318 #define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK BIT(1)
321 #define AUX_TX_REQUEST_READY_AUX_TX_P0 BIT(3)
323 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)
326 #define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(6)
327 #define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(5)
328 #define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(4)
329 #define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 BIT(3)
330 #define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 BIT(2)
331 #define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 BIT(1)
332 #define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 BIT(0)
348 #define PHY_FIFO_RST_AUX_TX_P0_MASK BIT(9)
349 #define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8)
351 #define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)
353 #define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8)
355 #define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1)
356 #define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0 BIT(2)
359 #define MTK_ATOP_EN_AUX_TX_P0 BIT(0)