Lines Matching +full:0 +full:x3400
9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
49 #define MTK_DP_1040 0x1040
52 #define RG_DPAUX_RX_EN BIT(0)
54 /* offset: TOP_OFFSET (0x2000) */
55 #define MTK_DP_TOP_PWR_STATE 0x2000
56 #define DP_PWR_STATE_MASK GENMASK(1, 0)
57 #define DP_PWR_STATE_BANDGAP BIT(0)
59 #define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)
60 #define MTK_DP_TOP_SWING_EMP 0x2004
61 #define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)
62 #define DP_TX0_VOLT_SWING_SHIFT 0
72 #define MTK_DP_TOP_RESET_AND_PROBE 0x2020
74 #define MTK_DP_TOP_IRQ_MASK 0x202c
76 #define MTK_DP_TOP_MEM_PD 0x2038
77 #define MEM_ISO_EN BIT(0)
80 /* offset: ENC0_OFFSET (0x3000) */
81 #define MTK_DP_ENC0_P0_3000 0x3000
82 #define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)
86 #define MTK_DP_ENC0_P0_3004 0x3004
89 #define MTK_DP_ENC0_P0_3010 0x3010
90 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
91 #define MTK_DP_ENC0_P0_3014 0x3014
92 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
93 #define MTK_DP_ENC0_P0_3018 0x3018
94 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
95 #define MTK_DP_ENC0_P0_301C 0x301c
96 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
97 #define MTK_DP_ENC0_P0_3020 0x3020
98 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
99 #define MTK_DP_ENC0_P0_3024 0x3024
100 #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
101 #define MTK_DP_ENC0_P0_3028 0x3028
102 #define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
104 #define MTK_DP_ENC0_P0_302C 0x302c
105 #define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
107 #define MTK_DP_ENC0_P0_3030 0x3030
108 #define HTOTAL_SEL_DP_ENC0_P0 BIT(0)
120 #define MTK_DP_ENC0_P0_3034 0x3034
121 #define MTK_DP_ENC0_P0_3038 0x3038
123 #define MTK_DP_ENC0_P0_303C 0x303c
124 #define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0)
126 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)
132 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << 12)
136 #define MTK_DP_ENC0_P0_3040 0x3040
137 #define SDP_DOWN_CNT_DP_ENC0_P0_VAL 0x20
138 #define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0)
139 #define MTK_DP_ENC0_P0_304C 0x304c
142 #define MTK_DP_ENC0_P0_3064 0x3064
143 #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
144 #define MTK_DP_ENC0_P0_3088 0x3088
150 #define MTK_DP_ENC0_P0_308C 0x308c
151 #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
152 #define MTK_DP_ENC0_P0_3090 0x3090
153 #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
154 #define MTK_DP_ENC0_P0_3094 0x3094
155 #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)
156 #define MTK_DP_ENC0_P0_30A4 0x30a4
157 #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)
158 #define MTK_DP_ENC0_P0_30A8 0x30a8
159 #define MTK_DP_ENC0_P0_30BC 0x30bc
160 #define ISRC_CONT_DP_ENC0_P0 BIT(0)
174 #define MTK_DP_ENC0_P0_30D8 0x30d8
175 #define MTK_DP_ENC0_P0_312C 0x312c
176 #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
178 #define MTK_DP_ENC0_P0_3154 0x3154
179 #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)
180 #define MTK_DP_ENC0_P0_3158 0x3158
181 #define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0)
182 #define MTK_DP_ENC0_P0_315C 0x315c
183 #define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
184 #define MTK_DP_ENC0_P0_3160 0x3160
185 #define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0)
186 #define MTK_DP_ENC0_P0_3164 0x3164
187 #define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
188 #define MTK_DP_ENC0_P0_3168 0x3168
189 #define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0)
190 #define MTK_DP_ENC0_P0_316C 0x316c
191 #define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0)
192 #define MTK_DP_ENC0_P0_3170 0x3170
193 #define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
194 #define MTK_DP_ENC0_P0_3174 0x3174
195 #define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0)
196 #define MTK_DP_ENC0_P0_3178 0x3178
197 #define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
198 #define MTK_DP_ENC0_P0_31B0 0x31b0
201 #define MTK_DP_ENC0_P0_31EC 0x31ec
205 /* offset: ENC1_OFFSET (0x3200) */
206 #define MTK_DP_ENC1_P0_3200 0x3200
207 #define MTK_DP_ENC1_P0_3280 0x3280
208 #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)
211 #define MTK_DP_ENC1_P0_3300 0x3300
214 #define MTK_DP_ENC1_P0_3304 0x3304
218 #define MTK_DP_ENC1_P0_3324 0x3324
220 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX 0
221 #define MTK_DP_ENC1_P0_3364 0x3364
222 #define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL 0x20
223 #define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0)
226 #define MTK_DP_ENC1_P0_3368 0x3368
227 #define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0)
238 #define MTK_DP_ENC1_P0_3374 0x3374
240 #define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)
242 #define MTK_DP_ENC1_P0_33F4 0x33f4
243 #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
246 /* offset: TRANS_OFFSET (0x3400) */
247 #define MTK_DP_TRANS_P0_3400 0x3400
252 #define MTK_DP_TRANS_P0_3404 0x3404
253 #define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0)
254 #define MTK_DP_TRANS_P0_340C 0x340c
256 #define MTK_DP_TRANS_P0_3410 0x3410
257 #define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0)
263 #define MTK_DP_TRANS_P0_3414 0x3414
265 #define MTK_DP_TRANS_P0_3418 0x3418
266 #define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0)
272 #define MTK_DP_TRANS_P0_342C 0x342c
273 #define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6))
274 #define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0)
275 #define MTK_DP_TRANS_P0_3430 0x3430
276 #define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)
278 #define MTK_DP_TRANS_P0_34A4 0x34a4
280 #define MTK_DP_TRANS_P0_3540 0x3540
281 #define FEC_EN_DP_TRANS_P0_MASK BIT(0)
283 #define MTK_DP_TRANS_P0_3580 0x3580
288 #define MTK_DP_TRANS_P0_35C8 0x35c8
289 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
290 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
291 #define MTK_DP_TRANS_P0_35D0 0x35d0
292 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
293 #define MTK_DP_TRANS_P0_35F0 0x35f0
297 /* offset: AUX_OFFSET (0x3600) */
298 #define MTK_DP_AUX_P0_360C 0x360c
299 #define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)
300 #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
301 #define MTK_DP_AUX_P0_3614 0x3614
302 #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
304 #define MTK_DP_AUX_P0_3618 0x3618
306 #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
307 #define MTK_DP_AUX_P0_3620 0x3620
310 #define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0)
311 #define MTK_DP_AUX_P0_3624 0x3624
312 #define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
313 #define MTK_DP_AUX_P0_3628 0x3628
314 #define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0)
315 #define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0)
316 #define MTK_DP_AUX_P0_362C 0x362c
317 #define AUX_NO_LENGTH_AUX_TX_P0 BIT(0)
320 #define MTK_DP_AUX_P0_3630 0x3630
322 #define MTK_DP_AUX_P0_3634 0x3634
325 #define MTK_DP_AUX_P0_3640 0x3640
332 #define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 BIT(0)
340 #define MTK_DP_AUX_P0_3644 0x3644
341 #define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
342 #define MTK_DP_AUX_P0_3648 0x3648
343 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
344 #define MTK_DP_AUX_P0_364C 0x364c
345 #define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)
346 #define MTK_DP_AUX_P0_3650 0x3650
350 #define MTK_DP_AUX_P0_3658 0x3658
351 #define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)
352 #define MTK_DP_AUX_P0_3690 0x3690
354 #define MTK_DP_AUX_P0_3704 0x3704
357 #define MTK_DP_AUX_P0_3708 0x3708
358 #define MTK_DP_AUX_P0_37C8 0x37c8
359 #define MTK_ATOP_EN_AUX_TX_P0 BIT(0)