51 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))  argument
52 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)  argument
53 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)  argument
77 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
79 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
189 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_register_vblank_cb()  local
191 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_register_vblank_cb()
192 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_register_vblank_cb()
197 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_unregister_vblank_cb()  local
199 	ovl->vblank_cb = NULL;  in mtk_ovl_unregister_vblank_cb()
200 	ovl->vblank_cb_data = NULL;  in mtk_ovl_unregister_vblank_cb()
205 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_enable_vblank()  local
207 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
208 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
213 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_disable_vblank()  local
215 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
220 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_blend_modes()  local
222 	return ovl->data->blend_modes;  in mtk_ovl_get_blend_modes()
227 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_formats()  local
229 	return ovl->data->formats;  in mtk_ovl_get_formats()
234 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_num_formats()  local
236 	return ovl->data->num_formats;  in mtk_ovl_get_num_formats()
241 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_enable()  local
243 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
248 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_disable()  local
250 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
255 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_start()  local
257 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
260 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
262 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
264 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
269 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_stop()  local
271 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
272 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
275 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
277 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
281 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,  in mtk_ovl_set_afbc()  argument
285 			   &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_set_afbc()
292 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_set_bit_depth()  local
295 	if (!ovl->data->supports_clrfmt_ext)  in mtk_ovl_set_bit_depth()
302 			   &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT,  in mtk_ovl_set_bit_depth()
310 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_config()  local
313 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
320 	mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,  in mtk_ovl_config()
321 			      ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
323 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
324 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
329 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_nr()  local
331 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
367 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_on()  local
369 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
372 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
374 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
375 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
381 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
382 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
389 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_off()  local
391 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
393 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
397 static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,  in mtk_ovl_fmt_convert()  argument
415 	if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))  in mtk_ovl_fmt_convert()
421 		return OVL_CON_CLRFMT_RGB565(ovl);  in mtk_ovl_fmt_convert()
423 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;  in mtk_ovl_fmt_convert()
425 		return OVL_CON_CLRFMT_RGB888(ovl);  in mtk_ovl_fmt_convert()
427 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;  in mtk_ovl_fmt_convert()
467 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_config()  local
495 	con = mtk_ovl_fmt_convert(ovl, state);  in mtk_ovl_layer_config()
526 	if (ovl->data->supports_afbc)  in mtk_ovl_layer_config()
527 		mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);  in mtk_ovl_layer_config()
529 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
532 			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));  in mtk_ovl_layer_config()
533 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
535 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
537 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
538 			      DISP_REG_OVL_ADDR(ovl, idx));  in mtk_ovl_layer_config()
541 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
542 				      DISP_REG_OVL_HDR_ADDR(ovl, idx));  in mtk_ovl_layer_config()
545 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
546 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
547 				      DISP_REG_OVL_HDR_PITCH(ovl, idx));  in mtk_ovl_layer_config()
551 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
560 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_on()  local
563 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
565 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
570 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_off()  local
573 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
575 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()