1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/soc/mediatek/mtk-cmdq.h>
51 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
52 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)
53 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)
77 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
79 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
156  * struct mtk_disp_ovl - DISP_OVL driver structure
157  * @crtc: associated crtc to report vblank events to
175 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);  in mtk_disp_ovl_irq_handler()
177 	if (!priv->vblank_cb)  in mtk_disp_ovl_irq_handler()
180 	priv->vblank_cb(priv->vblank_cb_data);  in mtk_disp_ovl_irq_handler()
191 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_register_vblank_cb()
192 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_register_vblank_cb()
199 	ovl->vblank_cb = NULL;  in mtk_ovl_unregister_vblank_cb()
200 	ovl->vblank_cb_data = NULL;  in mtk_ovl_unregister_vblank_cb()
207 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
208 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
215 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
222 	return ovl->data->blend_modes;  in mtk_ovl_get_blend_modes()
229 	return ovl->data->formats;  in mtk_ovl_get_formats()
236 	return ovl->data->num_formats;  in mtk_ovl_get_num_formats()
243 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
250 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
257 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
260 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
262 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
264 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
271 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
272 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
275 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
277 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
285 			   &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_set_afbc()
295 	if (!ovl->data->supports_clrfmt_ext)  in mtk_ovl_set_bit_depth()
302 			   &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT,  in mtk_ovl_set_bit_depth()
313 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
320 	mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,  in mtk_ovl_config()
321 			      ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
323 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
324 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
331 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
343 	struct drm_plane_state *state = &mtk_state->base;  in mtk_ovl_layer_check()
346 	if (state->rotation & ~mtk_ovl_supported_rotations(dev))  in mtk_ovl_layer_check()
347 		return -EINVAL;  in mtk_ovl_layer_check()
355 	if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0))  in mtk_ovl_layer_check()
356 		return -EINVAL;  in mtk_ovl_layer_check()
369 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
372 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
374 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
375 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
381 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
382 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
391 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
393 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
400 	unsigned int fmt = state->pending.format;  in mtk_ovl_fmt_convert()
413 	 * state->base.pixel_blend_mode should not be used.  in mtk_ovl_fmt_convert()
415 	if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))  in mtk_ovl_fmt_convert()
416 		blend_mode = state->base.pixel_blend_mode;  in mtk_ovl_fmt_convert()
468 	struct mtk_plane_pending_state *pending = &state->pending;  in mtk_ovl_layer_config()
469 	unsigned int addr = pending->addr;  in mtk_ovl_layer_config()
470 	unsigned int hdr_addr = pending->hdr_addr;  in mtk_ovl_layer_config()
471 	unsigned int pitch = pending->pitch;  in mtk_ovl_layer_config()
472 	unsigned int hdr_pitch = pending->hdr_pitch;  in mtk_ovl_layer_config()
473 	unsigned int fmt = pending->format;  in mtk_ovl_layer_config()
474 	unsigned int offset = (pending->y << 16) | pending->x;  in mtk_ovl_layer_config()
475 	unsigned int src_size = (pending->height << 16) | pending->width;  in mtk_ovl_layer_config()
476 	unsigned int blend_mode = state->base.pixel_blend_mode;  in mtk_ovl_layer_config()
479 	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;  in mtk_ovl_layer_config()
490 	if (!pending->enable) {  in mtk_ovl_layer_config()
496 	if (state->base.fb) {  in mtk_ovl_layer_config()
497 		con |= state->base.alpha & OVL_CON_ALPHA;  in mtk_ovl_layer_config()
503 		if (blend_mode || state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
512 		if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
516 	if (pending->rotation & DRM_MODE_REFLECT_Y) {  in mtk_ovl_layer_config()
518 		addr += (pending->height - 1) * pending->pitch;  in mtk_ovl_layer_config()
521 	if (pending->rotation & DRM_MODE_REFLECT_X) {  in mtk_ovl_layer_config()
523 		addr += pending->pitch - 1;  in mtk_ovl_layer_config()
526 	if (ovl->data->supports_afbc)  in mtk_ovl_layer_config()
529 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
532 			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));  in mtk_ovl_layer_config()
533 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
535 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
537 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
541 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
545 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
546 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
551 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_layer_config()
563 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
565 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
573 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
575 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
596 	struct device *dev = &pdev->dev;  in mtk_disp_ovl_probe()
604 		return -ENOMEM;  in mtk_disp_ovl_probe()
610 	priv->clk = devm_clk_get(dev, NULL);  in mtk_disp_ovl_probe()
611 	if (IS_ERR(priv->clk))  in mtk_disp_ovl_probe()
612 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in mtk_disp_ovl_probe()
616 	priv->regs = devm_ioremap_resource(dev, res);  in mtk_disp_ovl_probe()
617 	if (IS_ERR(priv->regs))  in mtk_disp_ovl_probe()
618 		return dev_err_probe(dev, PTR_ERR(priv->regs),  in mtk_disp_ovl_probe()
621 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_ovl_probe()
623 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_disp_ovl_probe()
626 	priv->data = of_device_get_match_data(dev);  in mtk_disp_ovl_probe()
647 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);  in mtk_disp_ovl_remove()
648 	pm_runtime_disable(&pdev->dev);  in mtk_disp_ovl_remove()
729 	{ .compatible = "mediatek,mt2701-disp-ovl",
731 	{ .compatible = "mediatek,mt8173-disp-ovl",
733 	{ .compatible = "mediatek,mt8183-disp-ovl",
735 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
737 	{ .compatible = "mediatek,mt8192-disp-ovl",
739 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
741 	{ .compatible = "mediatek,mt8195-disp-ovl",
751 		.name	= "mediatek-disp-ovl",