drm/mcde/mcde_dsi_regs.h

5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
41 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK 0x0000000F
43 #define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK 0x0003FFF0
45 #define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK 0xFFFC0000
47 #define DSI_MCTL_ULPOUT_TIME 0x00000018
48 #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT 0
49 #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK 0x000001FF
51 #define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK 0x0003FE00
53 #define DSI_MCTL_DPHY_STATIC 0x0000001C
54 #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK BIT(0)
61 #define DSI_MCTL_DPHY_STATIC_UI_X4_MASK 0x00000FC0
63 #define DSI_MCTL_MAIN_EN 0x00000020
64 #define DSI_MCTL_MAIN_EN_PLL_START BIT(0)
74 #define DSI_MCTL_MAIN_STS 0x00000024
75 #define DSI_MCTL_MAIN_STS_PLL_LOCK BIT(0)
84 #define DSI_MCTL_DPHY_ERR 0x00000028
85 #define DSI_INT_VID_RDDATA 0x00000030
86 #define DSI_INT_VID_GNT 0x00000034
87 #define DSI_INT_CMD_RDDATA 0x00000038
88 #define DSI_INT_CMD_GNT 0x0000003C
89 #define DSI_INT_INTERRUPT_CTL 0x00000040
91 #define DSI_CMD_MODE_CTL 0x00000050
92 #define DSI_CMD_MODE_CTL_IF1_ID_SHIFT 0
93 #define DSI_CMD_MODE_CTL_IF1_ID_MASK 0x00000003
95 #define DSI_CMD_MODE_CTL_IF2_ID_MASK 0x0000000C
101 #define DSI_CMD_MODE_CTL_FIL_VALUE_MASK 0x0000FF00
103 #define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK 0x03FF0000
105 #define DSI_CMD_MODE_STS 0x00000054
106 #define DSI_CMD_MODE_STS_ERR_NO_TE BIT(0)
113 #define DSI_DIRECT_CMD_SEND 0x00000060
115 #define DSI_DIRECT_CMD_MAIN_SETTINGS 0x00000064
116 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT 0
117 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK 0x00000007
118 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE 0
125 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK 0x00003F00
130 #define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK 0x0F000000
132 #define DSI_DIRECT_CMD_STS 0x00000068
133 #define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION BIT(0)
144 #define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK 0x00007800
147 #define DSI_DIRECT_CMD_STS_ACK_VAL_MASK 0xFFFF0000
149 #define DSI_DIRECT_CMD_RD_INIT 0x0000006C
150 #define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT 0
151 #define DSI_DIRECT_CMD_RD_INIT_RESET_MASK 0xFFFFFFFF
153 #define DSI_DIRECT_CMD_WRDAT0 0x00000070
154 #define DSI_DIRECT_CMD_WRDAT1 0x00000074
155 #define DSI_DIRECT_CMD_WRDAT2 0x00000078
156 #define DSI_DIRECT_CMD_WRDAT3 0x0000007C
158 #define DSI_DIRECT_CMD_RDDAT 0x00000080
160 #define DSI_DIRECT_CMD_RD_PROPERTY 0x00000084
161 #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT 0
162 #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK 0x0000FFFF
164 #define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK 0x00030000
166 #define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK 0x00040000
168 #define DSI_DIRECT_CMD_RD_STS 0x00000088
170 #define DSI_VID_MAIN_CTL 0x00000090
171 #define DSI_VID_MAIN_CTL_START_MODE_SHIFT 0
172 #define DSI_VID_MAIN_CTL_START_MODE_MASK 0x00000003
174 #define DSI_VID_MAIN_CTL_STOP_MODE_MASK 0x0000000C
176 #define DSI_VID_MAIN_CTL_VID_ID_MASK 0x00000030
178 #define DSI_VID_MAIN_CTL_HEADER_MASK 0x00000FC0
179 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS 0
186 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL 0
190 #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL 0
195 #define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK 0x00600000
197 #define DSI_VID_VSIZE 0x00000094
198 #define DSI_VID_VSIZE_VSA_LENGTH_SHIFT 0
199 #define DSI_VID_VSIZE_VSA_LENGTH_MASK 0x0000003F
201 #define DSI_VID_VSIZE_VBP_LENGTH_MASK 0x00000FC0
203 #define DSI_VID_VSIZE_VFP_LENGTH_MASK 0x000FF000
205 #define DSI_VID_VSIZE_VACT_LENGTH_MASK 0x7FF00000
207 #define DSI_VID_HSIZE1 0x00000098
208 #define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT 0
209 #define DSI_VID_HSIZE1_HSA_LENGTH_MASK 0x000003FF
211 #define DSI_VID_HSIZE1_HBP_LENGTH_MASK 0x000FFC00
213 #define DSI_VID_HSIZE1_HFP_LENGTH_MASK 0x7FF00000
215 #define DSI_VID_HSIZE2 0x0000009C
216 #define DSI_VID_HSIZE2_RGB_SIZE_SHIFT 0
217 #define DSI_VID_HSIZE2_RGB_SIZE_MASK 0x00001FFF
219 #define DSI_VID_BLKSIZE1 0x000000A0
220 #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT 0
221 #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK 0x00001FFF
223 #define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK 0x03FFE000
225 #define DSI_VID_BLKSIZE2 0x000000A4
226 #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT 0
227 #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK 0x00001FFF
229 #define DSI_VID_PCK_TIME 0x000000A8
230 #define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT 0
231 #define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK 0x00000FFF
233 #define DSI_VID_DPHY_TIME 0x000000AC
234 #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT 0
235 #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK 0x00001FFF
237 #define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK 0x00FFE000
239 #define DSI_VID_MODE_STS 0x000000BC
240 #define DSI_VID_MODE_STS_VSG_RUNNING BIT(0)
252 #define DSI_VID_VCA_SETTING1 0x000000C0
253 #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT 0
254 #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK 0x0000FFFF
257 #define DSI_VID_VCA_SETTING2 0x000000C4
258 #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT 0
259 #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK 0x0000FFFF
261 #define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK 0xFFFF0000
263 #define DSI_CMD_MODE_STS_CTL 0x000000F4
264 #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN BIT(0)
277 #define DSI_DIRECT_CMD_STS_CTL 0x000000F8
278 #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN BIT(0)
301 #define DSI_VID_MODE_STS_CTL 0x00000100
302 #define DSI_VID_MODE_STS_CTL_VSG_RUNNING BIT(0)
324 #define DSI_TG_STS_CTL 0x00000104
325 #define DSI_MCTL_DHPY_ERR_CTL 0x00000108
326 #define DSI_MCTL_MAIN_STS_CLR 0x00000110
328 #define DSI_CMD_MODE_STS_CLR 0x00000114
329 #define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR BIT(0)
336 #define DSI_DIRECT_CMD_STS_CLR 0x00000118
337 #define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR BIT(0)
349 #define DSI_DIRECT_CMD_RD_STS_CLR 0x0000011C
350 #define DSI_VID_MODE_STS_CLR 0x00000120
351 #define DSI_TG_STS_CLR 0x00000124
352 #define DSI_MCTL_DPHY_ERR_CLR 0x00000128
353 #define DSI_MCTL_MAIN_STS_FLAG 0x00000130
354 #define DSI_CMD_MODE_STS_FLAG 0x00000134
355 #define DSI_DIRECT_CMD_STS_FLAG 0x00000138
356 #define DSI_DIRECT_CMD_RD_STS_FLAG 0x0000013C
357 #define DSI_VID_MODE_STS_FLAG 0x00000140
358 #define DSI_TG_STS_FLAG 0x00000144
360 #define DSI_DPHY_LANES_TRIM 0x00000150
361 #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT 0
362 #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK 0x00000003
368 #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK 0x000000C0
370 #define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK 0x00000300
372 #define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK 0x00000C00
373 #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 0
383 #define DSI_ID_REG	0x00000FF0