13 	u32 cr;  member
24 	val = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
38 	writel(val, mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
87 	u32 cr;  in mcde_clk_div_recalc_rate()  local
98 	cr = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_recalc_rate()
99 	if (cr & MCDE_CRX1_BCD)  in mcde_clk_div_recalc_rate()
103 	div = cr & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_recalc_rate()
114 	u32 cr = 0;  in mcde_clk_div_set_rate()  local
122 		cr |= MCDE_CRX1_BCD;  in mcde_clk_div_set_rate()
125 		cr |= div & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_set_rate()
127 	cdiv->cr_div = cr;  in mcde_clk_div_set_rate()
173 	fifoa->cr = MCDE_CRA1;  in mcde_init_clock_divider()
183 	fifob->cr = MCDE_CRB1;  in mcde_init_clock_divider()