Lines Matching +full:0 +full:x10010000
24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
70 /* The DC get soft reset if this bit changed from "1" to "0", active low */
82 LSDC_DMA_STEP_256_BYTES = 0,
88 #define CFG_VALID_BITS_MASK GENMASK(20, 0)
95 #define HSYNC_START_MASK GENMASK(12, 0)
96 #define HSYNC_START_SHIFT 0
103 #define VSYNC_START_MASK GENMASK(11, 0)
104 #define VSYNC_START_SHIFT 0
107 #define LSDC_CRTC0_CFG_REG 0x1240
108 #define LSDC_CRTC0_FB0_ADDR_LO_REG 0x1260
109 #define LSDC_CRTC0_FB0_ADDR_HI_REG 0x15A0
110 #define LSDC_CRTC0_STRIDE_REG 0x1280
111 #define LSDC_CRTC0_FB_ORIGIN_REG 0x1300
112 #define LSDC_CRTC0_HDISPLAY_REG 0x1400
113 #define LSDC_CRTC0_HSYNC_REG 0x1420
114 #define LSDC_CRTC0_VDISPLAY_REG 0x1480
115 #define LSDC_CRTC0_VSYNC_REG 0x14A0
116 #define LSDC_CRTC0_GAMMA_INDEX_REG 0x14E0
117 #define LSDC_CRTC0_GAMMA_DATA_REG 0x1500
118 #define LSDC_CRTC0_FB1_ADDR_LO_REG 0x1580
119 #define LSDC_CRTC0_FB1_ADDR_HI_REG 0x15C0
122 #define LSDC_CRTC1_CFG_REG 0x1250
123 #define LSDC_CRTC1_FB0_ADDR_LO_REG 0x1270
124 #define LSDC_CRTC1_FB0_ADDR_HI_REG 0x15B0
125 #define LSDC_CRTC1_STRIDE_REG 0x1290
126 #define LSDC_CRTC1_FB_ORIGIN_REG 0x1310
127 #define LSDC_CRTC1_HDISPLAY_REG 0x1410
128 #define LSDC_CRTC1_HSYNC_REG 0x1430
129 #define LSDC_CRTC1_VDISPLAY_REG 0x1490
130 #define LSDC_CRTC1_VSYNC_REG 0x14B0
131 #define LSDC_CRTC1_GAMMA_INDEX_REG 0x14F0
132 #define LSDC_CRTC1_GAMMA_DATA_REG 0x1510
133 #define LSDC_CRTC1_FB1_ADDR_LO_REG 0x1590
134 #define LSDC_CRTC1_FB1_ADDR_HI_REG 0x15D0
140 #define PHY_DATA_EN BIT(0)
143 #define LSDC_CRTC0_DVO_CONF_REG 0x13C0
146 #define LSDC_CRTC1_DVO_CONF_REG 0x13D0
150 * of the CRTC, [31:16] : current X position, [15:0] : current Y position
152 #define LSDC_CRTC0_SCAN_POS_REG 0x14C0
153 #define LSDC_CRTC1_SCAN_POS_REG 0x14D0
159 #define SYNC_DEVIATION_NUM GENMASK(12, 0)
160 #define LSDC_CRTC0_SYNC_DEVIATION_REG 0x1B80
161 #define LSDC_CRTC1_SYNC_DEVIATION_REG 0x1B90
164 * In gross, LSDC_CRTC1_XXX_REG - LSDC_CRTC0_XXX_REG = 0x10, but not all of
170 #define CRTC_PIPE_OFFSET 0x10
178 #define CURSOR_FORMAT_MASK GENMASK(1, 0)
179 #define CURSOR_FORMAT_SHIFT 0
181 CURSOR_FORMAT_DISABLE = 0,
193 CURSOR_SIZE_32X32 = 0,
199 CURSOR_ON_CRTC0 = 0,
203 #define LSDC_CURSOR0_CFG_REG 0x1520
204 #define LSDC_CURSOR0_ADDR_LO_REG 0x1530
205 #define LSDC_CURSOR0_ADDR_HI_REG 0x15e0
206 #define LSDC_CURSOR0_POSITION_REG 0x1540 /* [31:16] Y, [15:0] X */
207 #define LSDC_CURSOR0_BG_COLOR_REG 0x1550 /* background color */
208 #define LSDC_CURSOR0_FG_COLOR_REG 0x1560 /* foreground color */
210 #define LSDC_CURSOR1_CFG_REG 0x1670
211 #define LSDC_CURSOR1_ADDR_LO_REG 0x1680
212 #define LSDC_CURSOR1_ADDR_HI_REG 0x16e0
213 #define LSDC_CURSOR1_POSITION_REG 0x1690 /* [31:16] Y, [15:0] X */
214 #define LSDC_CURSOR1_BG_COLOR_REG 0x16A0 /* background color */
215 #define LSDC_CURSOR1_FG_COLOR_REG 0x16B0 /* foreground color */
220 * Bits 15:0 inidicate the interrupt status
221 * Bits 31:16 control enable interrupts corresponding to bit 15:0 or not
222 * Write 1 to enable, write 0 to disable
228 * FBRF0: CRTC-0 reading from its framebuffer finished.
238 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
247 #define LSDC_INT_REG 0x1570
255 #define INT_CRTC1_VSYNC BIT(0)
273 #define INT_STATUS_MASK GENMASK(15, 0)
284 * GPIO data register, address offset: 0x1650
286 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
293 #define LS7A_DC_GPIO_DAT_REG 0x1650
296 * GPIO Input/Output direction control register, address offset: 0x1660
298 #define LS7A_DC_GPIO_DIR_REG 0x1660
308 #define LSDC_HDMI0_ZONE_REG 0x1700
309 #define LSDC_HDMI1_ZONE_REG 0x1710
311 #define HDMI_H_ZONE_IDLE_SHIFT 0
315 #define HDMI_INTERFACE_EN BIT(0)
328 /* 1: hw i2c, 0: gpio emu i2c, shouldn't put in LSDC_HDMIx_INTF_CTRL_REG */
331 #define LSDC_HDMI0_INTF_CTRL_REG 0x1720
332 #define LSDC_HDMI1_INTF_CTRL_REG 0x1730
334 #define HDMI_PHY_EN BIT(0)
340 #define LSDC_HDMI0_PHY_CTRL_REG 0x1800
341 #define LSDC_HDMI1_PHY_CTRL_REG 0x1810
344 #define HDMI_PLL_ENABLE BIT(0)
355 #define LSDC_HDMI0_PHY_PLL_REG 0x1820
356 #define LSDC_HDMI1_PHY_PLL_REG 0x1830
361 #define LSDC_HDMI_HPD_STATUS_REG 0x1BA0
362 #define HDMI0_HPD_FLAG BIT(0)
365 #define LSDC_HDMI0_PHY_CAL_REG 0x18C0
366 #define LSDC_HDMI1_PHY_CAL_REG 0x18D0
369 #define LSDC_HDMI0_AVI_CONTENT0 0x18E0
370 #define LSDC_HDMI1_AVI_CONTENT0 0x18D0
371 #define LSDC_HDMI0_AVI_CONTENT1 0x1900
372 #define LSDC_HDMI1_AVI_CONTENT1 0x1910
373 #define LSDC_HDMI0_AVI_CONTENT2 0x1920
374 #define LSDC_HDMI1_AVI_CONTENT2 0x1930
375 #define LSDC_HDMI0_AVI_CONTENT3 0x1940
376 #define LSDC_HDMI1_AVI_CONTENT3 0x1950
378 /* 1: enable avi infoframe packet, 0: disable avi infoframe packet */
379 #define AVI_PKT_ENABLE BIT(0)
380 /* 1: send one every two frame, 0: send one each frame */
388 #define LSDC_HDMI0_AVI_INFO_CRTL_REG 0x1960
389 #define LSDC_HDMI1_AVI_INFO_CRTL_REG 0x1970
394 #define LSDC_CRTC0_VSYNC_COUNTER_REG 0x1A00
395 #define LSDC_CRTC1_VSYNC_COUNTER_REG 0x1A10
400 #define LSDC_HDMI0_AUDIO_PLL_LO_REG 0x1A20
401 #define LSDC_HDMI1_AUDIO_PLL_LO_REG 0x1A30
403 #define LSDC_HDMI0_AUDIO_PLL_HI_REG 0x1A40
404 #define LSDC_HDMI1_AUDIO_PLL_HI_REG 0x1A50