Lines Matching +full:8 +full:m
24 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8)
25 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8)
26 #define LCD_CTRL_ALPHA_TOP_GL1 (2 << 8)
27 #define LCD_CTRL_ALPHA_TOP_GL2 (3 << 8)
61 #define LAYER0_DMA_CB_FIFO_UNDERFLOW BIT(8)
124 #define LCD_LAYER_TRANSPARENT_EN BIT(8)
133 #define LCD_LAYER_FORMAT_RGBX8888 (8 << 9)
243 #define LCD_DMA_LAYER_AXI_BURST_8 (8 << 5)
400 #define HS_OFFSET(M) (((M) + 1) * 0x400) argument
403 #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) argument
410 #define LCD_VC(ch) ((ch) << 8)
417 #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ argument
418 + HS_OFFSET(M))
426 #define DSI_SYNC_PULSE_EVENTN BIT(8)
435 #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ argument
436 HS_OFFSET(M) + (0x2C * (N)) \
437 + (8 * (O)))
448 #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ argument
450 + HS_OFFSET(M) + (0x2C * (N)))
452 #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ argument
453 (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \
454 + (0x2C * (N)) + (8 * (O)))
457 #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ argument
458 (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \
461 #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ argument
462 (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \
465 #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ argument
466 (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \
469 #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ argument
470 (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \
473 #define MIPI_TXm_HS_V_ACTIVEn(M, N) \ argument
474 (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \
477 #define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \ argument
478 (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \
481 #define MIPI_TXm_HS_H_BACKPORCHn(M, N) \ argument
482 (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \
485 #define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \ argument
486 (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \
489 #define MIPI_TXm_HS_H_ACTIVEn(M, N) \ argument
490 (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \
493 #define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \ argument
494 (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \
497 #define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \ argument
498 (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \
501 #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \ argument
502 (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \
506 #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \ argument
507 (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M))
511 #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ argument
512 (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \
520 #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ argument
521 (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \
545 #define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \ argument
547 (M) + (N))
554 #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \ argument
555 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, (M) + (N))
557 #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ argument
558 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, (M) + (N))
561 #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ argument
562 HS_OFFSET(M))
563 #define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \ argument
564 MIPI_TX_HS_IRQ_STATUSm(M))
572 #define MIPI_TX_HS_IRQ_DMA_DONE_1 BIT(8)
618 #define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \ argument
620 + HS_OFFSET(M))
625 #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ argument
626 (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M))
627 #define TP_EN_VCm(M) (1 << ((M) * 0x04)) argument
628 #define TP_SEL_VCm(M, N) \ argument
629 ((N) << (((M) * 0x04) + 1))
630 #define TP_STRIPE_WIDTH(M) ((M) << 16) argument
632 #define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \ argument
633 (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M))
635 #define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \ argument
636 (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M))
661 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val)
670 (((dphy % 4) * 8) + 4)) & 0x03)
692 4, ((val) << (((dphy) % 4) * 8)))
696 >> (((dphy) % 4) * 8) & 0xff)
700 >> (((dphy) % 4) * 8) & 0xff)