Lines Matching +full:max +full:- +full:channels +full:- +full:clocked
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
178 clk_disable_unprepare(kmb_dsi->clk_mipi); in kmb_dsi_clk_disable()
179 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_disable()
180 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_disable()
186 mipi_dsi_host_unregister(kmb_dsi->host); in kmb_dsi_host_unregister()
225 return -ENOMEM; in kmb_dsi_host_bridge_init()
227 dsi_host->ops = &kmb_dsi_host_ops; in kmb_dsi_host_bridge_init()
233 return -ENOMEM; in kmb_dsi_host_bridge_init()
237 dsi_host->dev = dev; in kmb_dsi_host_bridge_init()
242 dsi_out = of_graph_get_endpoint_by_regs(dev->of_node, 0, 1); in kmb_dsi_host_bridge_init()
245 return -EINVAL; in kmb_dsi_host_bridge_init()
251 return -EINVAL; in kmb_dsi_host_bridge_init()
259 return -EPROBE_DEFER; in kmb_dsi_host_bridge_init()
284 return -EINVAL; in mipi_get_datatype_params()
304 return -EINVAL; in mipi_get_datatype_params()
321 return -EINVAL; in mipi_get_datatype_params()
340 return -EINVAL; in mipi_get_datatype_params()
364 return -EINVAL; in mipi_get_datatype_params()
396 cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; in mipi_tx_fg_section_cfg_regs()
399 cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) in mipi_tx_fg_section_cfg_regs()
403 cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK) in mipi_tx_fg_section_cfg_regs()
407 cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) in mipi_tx_fg_section_cfg_regs()
409 if (ph_cfg->dma_packed) in mipi_tx_fg_section_cfg_regs()
412 dev_dbg(kmb_dsi->dev, in mipi_tx_fg_section_cfg_regs()
414 ctrl_no, frame_id, section, cfg, ph_cfg->dma_packed); in mipi_tx_fg_section_cfg_regs()
424 * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 in mipi_tx_fg_section_cfg_regs()
425 * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 in mipi_tx_fg_section_cfg_regs()
432 dev_dbg(kmb_dsi->dev, in mipi_tx_fg_section_cfg_regs()
434 ph_cfg->wc); in mipi_tx_fg_section_cfg_regs()
452 ret = mipi_get_datatype_params(frame_scfg->data_type, in mipi_tx_fg_section_cfg()
453 frame_scfg->data_mode, in mipi_tx_fg_section_cfg()
461 if (frame_scfg->width_pixels % in mipi_tx_fg_section_cfg()
463 return -EINVAL; in mipi_tx_fg_section_cfg()
465 *wc = compute_wc(frame_scfg->width_pixels, in mipi_tx_fg_section_cfg()
471 ph_cfg.data_mode = frame_scfg->data_mode; in mipi_tx_fg_section_cfg()
472 ph_cfg.data_type = frame_scfg->data_type; in mipi_tx_fg_section_cfg()
473 ph_cfg.dma_packed = frame_scfg->dma_packed; in mipi_tx_fg_section_cfg()
477 frame_scfg->height_lines, in mipi_tx_fg_section_cfg()
500 if (kmb_dsi->sys_clk_mhz == SYSCLK_500) { in mipi_tx_fg_cfg_regs()
501 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW; in mipi_tx_fg_cfg_regs()
504 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI; in mipi_tx_fg_cfg_regs()
507 /* PPL-Pixel Packing Layer, LLP-Low Level Protocol in mipi_tx_fg_cfg_regs()
508 * Frame genartor timing parameters are clocked on the system clock, in mipi_tx_fg_cfg_regs()
509 * whereas as the equivalent parameters in the LLP blocks are clocked in mipi_tx_fg_cfg_regs()
510 * on LLP Tx clock from the D-PHY - BYTE clock in mipi_tx_fg_cfg_regs()
514 ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / in mipi_tx_fg_cfg_regs()
515 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
517 dev_dbg(kmb_dsi->dev, "ppl_llp_ratio=%d\n", ppl_llp_ratio); in mipi_tx_fg_cfg_regs()
518 dev_dbg(kmb_dsi->dev, "bpp=%d sysclk=%d lane-rate=%d active-lanes=%d\n", in mipi_tx_fg_cfg_regs()
519 fg_cfg->bpp, sysclk, fg_cfg->lane_rate_mbps, in mipi_tx_fg_cfg_regs()
520 fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
524 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->v_active); in mipi_tx_fg_cfg_regs()
528 * channels 0-3) in mipi_tx_fg_cfg_regs()
529 * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 in mipi_tx_fg_cfg_regs()
530 * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 in mipi_tx_fg_cfg_regs()
534 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->vsync_width); in mipi_tx_fg_cfg_regs()
538 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_backporch); in mipi_tx_fg_cfg_regs()
542 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_frontporch); in mipi_tx_fg_cfg_regs()
546 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_active); in mipi_tx_fg_cfg_regs()
551 (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
556 (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
561 (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); in mipi_tx_fg_cfg_regs()
567 val = (fg_cfg->h_active * sysclk * 1000) / in mipi_tx_fg_cfg_regs()
568 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); in mipi_tx_fg_cfg_regs()
574 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
578 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
583 fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); in mipi_tx_fg_cfg_regs()
597 if (fg_cfg->sections[i]) in mipi_tx_fg_cfg()
598 fg_num_lines += fg_cfg->sections[i]->height_lines; in mipi_tx_fg_cfg()
603 fg_t_cfg.hsync_width = fg_cfg->hsync_width; in mipi_tx_fg_cfg()
604 fg_t_cfg.h_backporch = fg_cfg->h_backporch; in mipi_tx_fg_cfg()
605 fg_t_cfg.h_frontporch = fg_cfg->h_frontporch; in mipi_tx_fg_cfg()
607 fg_t_cfg.vsync_width = fg_cfg->vsync_width; in mipi_tx_fg_cfg()
608 fg_t_cfg.v_backporch = fg_cfg->v_backporch; in mipi_tx_fg_cfg()
609 fg_t_cfg.v_frontporch = fg_cfg->v_frontporch; in mipi_tx_fg_cfg()
632 MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; in mipi_tx_multichannel_fifo_cfg()
634 /* MC fifo size for virtual channels 0-3 in mipi_tx_multichannel_fifo_cfg()
635 * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 in mipi_tx_multichannel_fifo_cfg()
636 * REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 in mipi_tx_multichannel_fifo_cfg()
656 if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) in mipi_tx_ctrl_cfg()
658 if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) in mipi_tx_ctrl_cfg()
660 if (ctrl_cfg->tx_ctrl_cfg.line_counter_active) in mipi_tx_ctrl_cfg()
662 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking) in mipi_tx_ctrl_cfg()
664 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) in mipi_tx_ctrl_cfg()
666 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) in mipi_tx_ctrl_cfg()
668 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) in mipi_tx_ctrl_cfg()
670 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn) in mipi_tx_ctrl_cfg()
672 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line) in mipi_tx_ctrl_cfg()
674 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) in mipi_tx_ctrl_cfg()
681 if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) in mipi_tx_ctrl_cfg()
683 if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) in mipi_tx_ctrl_cfg()
686 dev_dbg(kmb_dsi->dev, "sync_cfg=%d fg_en=%d\n", sync_cfg, fg_en); in mipi_tx_ctrl_cfg()
693 ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); in mipi_tx_ctrl_cfg()
694 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) in mipi_tx_ctrl_cfg()
696 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) in mipi_tx_ctrl_cfg()
725 frame = ctrl_cfg->tx_ctrl_cfg.frames[frame_id]; in mipi_tx_init_cntrl()
732 /* TODO - assume there is only one valid section in a frame, in mipi_tx_init_cntrl()
736 if (!frame->sections[sect]) in mipi_tx_init_cntrl()
740 frame->sections[sect], in mipi_tx_init_cntrl()
748 mipi_tx_fg_cfg(kmb_dsi, frame_id, ctrl_cfg->active_lanes, in mipi_tx_init_cntrl()
750 ctrl_cfg->lane_rate_mbps, frame); in mipi_tx_init_cntrl()
761 return -EINVAL; in mipi_tx_init_cntrl()
762 /* Multi-Channel FIFO Configuration */ in mipi_tx_init_cntrl()
763 mipi_tx_multichannel_fifo_cfg(kmb_dsi, ctrl_cfg->active_lanes, frame_id); in mipi_tx_init_cntrl()
775 * - set testclk HIGH in test_mode_send()
776 * - set testdin with test code in test_mode_send()
777 * - set testen HIGH in test_mode_send()
778 * - set testclk LOW in test_mode_send()
779 * - set testen LOW in test_mode_send()
799 * - set testen LOW in test_mode_send()
800 * - set testclk LOW in test_mode_send()
801 * - set testdin with data in test_mode_send()
802 * - set testclk HIGH in test_mode_send()
854 if (vco->freq < vco_table[i].freq) { in mipi_tx_get_vco_params()
860 WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); in mipi_tx_get_vco_params()
870 /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz in mipi_tx_pll_setup()
871 * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) in mipi_tx_pll_setup()
872 * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) in mipi_tx_pll_setup()
873 * n: - valid range [0 15] in mipi_tx_pll_setup()
874 * N: - N = n + 1 in mipi_tx_pll_setup()
875 * -valid range: [1 16] in mipi_tx_pll_setup()
876 * -conditions: - (pll_ref_clk / N) >= 2 MHz in mipi_tx_pll_setup()
877 * -(pll_ref_clk / N) <= 8 MHz in mipi_tx_pll_setup()
879 * M: - M = m + 2 in mipi_tx_pll_setup()
880 * -valid range [64 625] in mipi_tx_pll_setup()
881 * -Fvco = (M/N) * pll_ref_clk in mipi_tx_pll_setup()
894 * multiply by 1000 for precision - in mipi_tx_pll_setup()
911 /* Trim the potential pll freq to max supported */ in mipi_tx_pll_setup()
915 delta = abs(freq - target_freq_mhz); in mipi_tx_pll_setup()
936 dev_dbg(kmb_dsi->dev, "m = %d n = %d\n", best_m, best_n); in mipi_tx_pll_setup()
942 /* m - low nibble PLL_Loop_Divider_Ratio[4:0] in mipi_tx_pll_setup()
948 /* m - high nibble PLL_Loop_Divider_Ratio[4:0] in mipi_tx_pll_setup()
958 /* Program Charge-Pump parameters */ in mipi_tx_pll_setup()
960 /* pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ in mipi_tx_pll_setup()
966 /* pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ in mipi_tx_pll_setup()
970 /* pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ in mipi_tx_pll_setup()
973 /* pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ in mipi_tx_pll_setup()
976 /* pll_th1 -Lock Detector Phase error threshold, in mipi_tx_pll_setup()
983 /* pll_th2 - Lock Filter length, document gives fixed value */ in mipi_tx_pll_setup()
986 /* pll_th3- PLL Unlocking filter, document gives fixed value */ in mipi_tx_pll_setup()
989 /* pll_lock_sel-PLL Lock Detector Selection, in mipi_tx_pll_setup()
1015 /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON in set_slewrate_gt_1000()
1052 * - slew rate control ON in set_slewrate_lt_1000()
1053 * - typical rise/fall times: 225 ps in set_slewrate_lt_1000()
1088 mipi_tx_pll_setup(kmb_dsi, dphy_no, cfg->ref_clk_khz / 1000, in setup_pll()
1089 cfg->lane_rate_mbps / 2); in setup_pll()
1105 cfg->lane_rate_mbps) in set_lane_data_rate()
1124 /* Set D-PHY in shutdown mode */ in dphy_init_sequence()
1132 /* Init D-PHY_n in dphy_init_sequence()
1133 * Pulse testclear signal to make sure the d-phy configuration in dphy_init_sequence()
1143 /* Set mastermacro bit - Master or slave mode */ in dphy_init_sequence()
1158 /* High-Speed Tx Slew Rate Calibration in dphy_init_sequence()
1161 if (cfg->lane_rate_mbps > 1500) in dphy_init_sequence()
1163 else if (cfg->lane_rate_mbps > 1000) in dphy_init_sequence()
1169 val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; in dphy_init_sequence()
1172 /* Enable config clk for the corresponding d-phy */ in dphy_init_sequence()
1185 * NOTE: basedir only applies to LANE_0 of each D-PHY. in dphy_init_sequence()
1186 * The other lanes keep their direction based on the D-PHY type, in dphy_init_sequence()
1188 * bits[5:0] - BaseDir: 1 = Rx in dphy_init_sequence()
1189 * bits[9:6] - BaseDir: 0 = Tx in dphy_init_sequence()
1196 * set for the D-PHY (Rx/Tx) in dphy_init_sequence()
1202 ((1 << active_lanes) - 1)); in dphy_init_sequence()
1206 /* Take D-PHY out of shutdown mode */ in dphy_init_sequence()
1233 dev_dbg(kmb_dsi->dev, "%s: dphy %d val = %x", __func__, dphy_no, val); in dphy_wait_fsm()
1234 dev_dbg(kmb_dsi->dev, "* DPHY %d WAIT_FSM %s *", in dphy_wait_fsm()
1242 u32 data_lanes = (1 << active_lanes) - 1; in wait_init_done()
1250 /* TODO-need to add a time out and return failure */ in wait_init_done()
1255 dev_dbg(kmb_dsi->dev, in wait_init_done()
1262 dev_dbg(kmb_dsi->dev, "* DPHY %d INIT - %s *", in wait_init_done()
1272 /* TODO-need to add a time out and return failure */ in wait_pll_lock()
1276 dev_dbg(kmb_dsi->dev, "%s: timing out", __func__); in wait_pll_lock()
1281 dev_dbg(kmb_dsi->dev, "* PLL Locked for DPHY %d - %s *", in wait_pll_lock()
1290 /* Multiple D-PHYs needed */ in mipi_tx_init_dphy()
1291 if (cfg->active_lanes > MIPI_DPHY_D_LANES) { in mipi_tx_init_dphy()
1296 * b1. reg addr 0x03[3:0] - state_main[3:0] == 5 (LOCK) in mipi_tx_init_dphy()
1299 * - rescal_done in mipi_tx_init_dphy()
1301 * addr 0xA7[3:2] - srcal_done, sr_finished in mipi_tx_init_dphy()
1309 (cfg->active_lanes - MIPI_DPHY_D_LANES), in mipi_tx_init_dphy()
1320 cfg->active_lanes - MIPI_DPHY_D_LANES); in mipi_tx_init_dphy()
1325 dphy_init_sequence(kmb_dsi, cfg, dphy_no, cfg->active_lanes, in mipi_tx_init_dphy()
1328 wait_init_done(kmb_dsi, dphy_no, cfg->active_lanes); in mipi_tx_init_dphy()
1340 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam"); in connect_lcd_to_mipi()
1342 dev_dbg(kmb_dsi->dev, "failed to get msscam syscon"); in connect_lcd_to_mipi()
1346 /* DISABLE MIPI->CIF CONNECTION */ in connect_lcd_to_mipi()
1349 /* ENABLE LCD->MIPI CONNECTION */ in connect_lcd_to_mipi()
1351 /* DISABLE LCD->CIF LOOPBACK */ in connect_lcd_to_mipi()
1360 kmb_dsi->sys_clk_mhz = sys_clk_mhz; in kmb_dsi_mode_set()
1363 mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; in kmb_dsi_mode_set()
1364 mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; in kmb_dsi_mode_set()
1366 mode->crtc_vsync_end - mode->crtc_vsync_start; in kmb_dsi_mode_set()
1368 mode->crtc_vtotal - mode->crtc_vsync_end; in kmb_dsi_mode_set()
1370 mode->crtc_vsync_start - mode->crtc_vdisplay; in kmb_dsi_mode_set()
1372 mode->crtc_hsync_end - mode->crtc_hsync_start; in kmb_dsi_mode_set()
1374 mode->crtc_htotal - mode->crtc_hsync_end; in kmb_dsi_mode_set()
1376 mode->crtc_hsync_start - mode->crtc_hdisplay; in kmb_dsi_mode_set()
1381 data_rate = ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) * in kmb_dsi_mode_set()
1385 dev_dbg(kmb_dsi->dev, "data_rate=%u active_lanes=%d\n", in kmb_dsi_mode_set()
1405 dev_info(kmb_dsi->dev, "mipi hw initialized"); in kmb_dsi_mode_set()
1413 struct device *dev = get_device(&pdev->dev); in kmb_dsi_init()
1418 return ERR_PTR(-ENOMEM); in kmb_dsi_init()
1421 kmb_dsi->host = dsi_host; in kmb_dsi_init()
1422 kmb_dsi->host->ops = &kmb_dsi_host_ops; in kmb_dsi_init()
1424 dsi_device->host = kmb_dsi->host; in kmb_dsi_init()
1425 kmb_dsi->device = dsi_device; in kmb_dsi_init()
1436 encoder = &kmb_dsi->base; in kmb_dsi_encoder_init()
1437 encoder->possible_crtcs = 1; in kmb_dsi_encoder_init()
1438 encoder->possible_clones = 0; in kmb_dsi_encoder_init()
1442 dev_err(kmb_dsi->dev, "Failed to init encoder %d\n", ret); in kmb_dsi_encoder_init()
1467 struct device *dev = kmb_dsi->dev; in kmb_dsi_map_mmio()
1469 res = platform_get_resource_byname(kmb_dsi->pdev, IORESOURCE_MEM, in kmb_dsi_map_mmio()
1473 return -ENOMEM; in kmb_dsi_map_mmio()
1475 kmb_dsi->mipi_mmio = devm_ioremap_resource(dev, res); in kmb_dsi_map_mmio()
1476 if (IS_ERR(kmb_dsi->mipi_mmio)) { in kmb_dsi_map_mmio()
1478 return PTR_ERR(kmb_dsi->mipi_mmio); in kmb_dsi_map_mmio()
1486 struct device *dev = kmb_dsi->dev; in kmb_dsi_clk_enable()
1488 ret = clk_prepare_enable(kmb_dsi->clk_mipi); in kmb_dsi_clk_enable()
1494 ret = clk_prepare_enable(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_enable()
1500 ret = clk_prepare_enable(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_enable()
1512 struct device *dev = kmb_dsi->dev; in kmb_dsi_clk_init()
1515 kmb_dsi->clk_mipi = devm_clk_get(dev, "clk_mipi"); in kmb_dsi_clk_init()
1516 if (IS_ERR(kmb_dsi->clk_mipi)) { in kmb_dsi_clk_init()
1518 return PTR_ERR(kmb_dsi->clk_mipi); in kmb_dsi_clk_init()
1521 kmb_dsi->clk_mipi_ecfg = devm_clk_get(dev, "clk_mipi_ecfg"); in kmb_dsi_clk_init()
1522 if (IS_ERR(kmb_dsi->clk_mipi_ecfg)) { in kmb_dsi_clk_init()
1524 return PTR_ERR(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1527 kmb_dsi->clk_mipi_cfg = devm_clk_get(dev, "clk_mipi_cfg"); in kmb_dsi_clk_init()
1528 if (IS_ERR(kmb_dsi->clk_mipi_cfg)) { in kmb_dsi_clk_init()
1530 return PTR_ERR(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1533 clk_set_rate(kmb_dsi->clk_mipi, KMB_MIPI_DEFAULT_CLK); in kmb_dsi_clk_init()
1534 if (clk_get_rate(kmb_dsi->clk_mipi) != KMB_MIPI_DEFAULT_CLK) { in kmb_dsi_clk_init()
1537 return -1; in kmb_dsi_clk_init()
1539 dev_dbg(dev, "clk_mipi = %ld\n", clk_get_rate(kmb_dsi->clk_mipi)); in kmb_dsi_clk_init()
1541 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1544 clk_set_rate(kmb_dsi->clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); in kmb_dsi_clk_init()
1545 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_init()
1549 return -1; in kmb_dsi_clk_init()
1553 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1556 clk_set_rate(kmb_dsi->clk_mipi_cfg, 24000000); in kmb_dsi_clk_init()
1557 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_init()
1561 return -1; in kmb_dsi_clk_init()