98 static void dcss_dtg_write(struct dcss_dtg *dtg, u32 val, u32 ofs)  in dcss_dtg_write()  argument
100 	if (!dtg->in_use)  in dcss_dtg_write()
101 		dcss_writel(val, dtg->base_reg + ofs);  in dcss_dtg_write()
103 	dcss_ctxld_write(dtg->ctxld, dtg->ctx_id,  in dcss_dtg_write()
104 			 val, dtg->base_ofs + ofs);  in dcss_dtg_write()
109 	struct dcss_dtg *dtg = data;  in dcss_dtg_irq_handler()  local
112 	status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_irq_handler()
117 	dcss_ctxld_kick(dtg->ctxld);  in dcss_dtg_irq_handler()
119 	dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_irq_handler()
124 static int dcss_dtg_irq_config(struct dcss_dtg *dtg,  in dcss_dtg_irq_config()  argument
129 	dtg->ctxld_kick_irq = platform_get_irq_byname(pdev, "ctxld_kick");  in dcss_dtg_irq_config()
130 	if (dtg->ctxld_kick_irq < 0)  in dcss_dtg_irq_config()
131 		return dtg->ctxld_kick_irq;  in dcss_dtg_irq_config()
134 		    dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_irq_config()
136 	ret = request_irq(dtg->ctxld_kick_irq, dcss_dtg_irq_handler,  in dcss_dtg_irq_config()
137 			  0, "dcss_ctxld_kick", dtg);  in dcss_dtg_irq_config()
139 		dev_err(dtg->dev, "dtg: irq request failed.\n");  in dcss_dtg_irq_config()
143 	disable_irq(dtg->ctxld_kick_irq);  in dcss_dtg_irq_config()
145 	dtg->ctxld_kick_irq_en = false;  in dcss_dtg_irq_config()
153 	struct dcss_dtg *dtg;  in dcss_dtg_init()  local
155 	dtg = devm_kzalloc(dcss->dev, sizeof(*dtg), GFP_KERNEL);  in dcss_dtg_init()
156 	if (!dtg)  in dcss_dtg_init()
159 	dcss->dtg = dtg;  in dcss_dtg_init()
160 	dtg->dev = dcss->dev;  in dcss_dtg_init()
161 	dtg->ctxld = dcss->ctxld;  in dcss_dtg_init()
163 	dtg->base_reg = devm_ioremap(dtg->dev, dtg_base, SZ_4K);  in dcss_dtg_init()
164 	if (!dtg->base_reg) {  in dcss_dtg_init()
165 		dev_err(dtg->dev, "dtg: unable to remap dtg base\n");  in dcss_dtg_init()
169 	dtg->base_ofs = dtg_base;  in dcss_dtg_init()
170 	dtg->ctx_id = CTX_DB;  in dcss_dtg_init()
172 	dtg->alpha = 255;  in dcss_dtg_init()
174 	dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |  in dcss_dtg_init()
175 		((dtg->alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_init()
177 	ret = dcss_dtg_irq_config(dtg, to_platform_device(dtg->dev));  in dcss_dtg_init()
182 void dcss_dtg_exit(struct dcss_dtg *dtg)  in dcss_dtg_exit()  argument
184 	free_irq(dtg->ctxld_kick_irq, dtg);  in dcss_dtg_exit()
187 void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)  in dcss_dtg_sync_set()  argument
189 	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dtg->dev);  in dcss_dtg_sync_set()
213 		dev_info(dtg->dev,  in dcss_dtg_sync_set()
218 	dcss_dtg_write(dtg, ((dtg_lrc_y << TC_Y_POS) | dtg_lrc_x),  in dcss_dtg_sync_set()
220 	dcss_dtg_write(dtg, ((dis_ulc_y << TC_Y_POS) | dis_ulc_x),  in dcss_dtg_sync_set()
222 	dcss_dtg_write(dtg, ((dis_lrc_y << TC_Y_POS) | dis_lrc_x),  in dcss_dtg_sync_set()
225 	dtg->dis_ulc_x = dis_ulc_x;  in dcss_dtg_sync_set()
226 	dtg->dis_ulc_y = dis_ulc_y;  in dcss_dtg_sync_set()
233 	dcss_dtg_write(dtg, sb_ctxld_trig | db_ctxld_trig, DCSS_DTG_TC_CTXLD);  in dcss_dtg_sync_set()
236 	dcss_dtg_write(dtg, 0, DCSS_DTG_LINE1_INT);  in dcss_dtg_sync_set()
239 	dcss_dtg_write(dtg, ((90 * dis_lrc_y) / 100) << 16, DCSS_DTG_LINE0_INT);  in dcss_dtg_sync_set()
242 void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,  in dcss_dtg_plane_pos_set()  argument
248 	p_ulc_x = dtg->dis_ulc_x + px;  in dcss_dtg_plane_pos_set()
249 	p_ulc_y = dtg->dis_ulc_y + py;  in dcss_dtg_plane_pos_set()
254 		dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_TOP + 0x8 * ch_num);  in dcss_dtg_plane_pos_set()
255 		dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_BOT + 0x8 * ch_num);  in dcss_dtg_plane_pos_set()
257 		dcss_dtg_write(dtg, ((p_ulc_y << TC_Y_POS) | p_ulc_x),  in dcss_dtg_plane_pos_set()
259 		dcss_dtg_write(dtg, ((p_lrc_y << TC_Y_POS) | p_lrc_x),  in dcss_dtg_plane_pos_set()
264 bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha)  in dcss_dtg_global_alpha_changed()  argument
269 	return alpha != dtg->alpha;  in dcss_dtg_global_alpha_changed()
272 void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,  in dcss_dtg_plane_alpha_set()  argument
284 		dtg->alpha_cfg = (alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK;  in dcss_dtg_plane_alpha_set()
286 		dtg->alpha_cfg = CH1_ALPHA_SEL;  in dcss_dtg_plane_alpha_set()
288 	dtg->alpha = alpha;  in dcss_dtg_plane_alpha_set()
291 void dcss_dtg_css_set(struct dcss_dtg *dtg)  in dcss_dtg_css_set()  argument
293 	dtg->control_status |=  in dcss_dtg_css_set()
297 void dcss_dtg_enable(struct dcss_dtg *dtg)  in dcss_dtg_enable()  argument
299 	dtg->control_status |= DTG_START;  in dcss_dtg_enable()
301 	dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_enable()
302 	dtg->control_status |= dtg->alpha_cfg;  in dcss_dtg_enable()
304 	dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_enable()
306 	dtg->in_use = true;  in dcss_dtg_enable()
309 void dcss_dtg_shutoff(struct dcss_dtg *dtg)  in dcss_dtg_shutoff()  argument
311 	dtg->control_status &= ~DTG_START;  in dcss_dtg_shutoff()
313 	dcss_writel(dtg->control_status,  in dcss_dtg_shutoff()
314 		    dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_shutoff()
316 	dtg->in_use = false;  in dcss_dtg_shutoff()
319 bool dcss_dtg_is_enabled(struct dcss_dtg *dtg)  in dcss_dtg_is_enabled()  argument
321 	return dtg->in_use;  in dcss_dtg_is_enabled()
324 void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en)  in dcss_dtg_ch_enable()  argument
329 	control_status = dtg->control_status & ~ch_en_map[ch_num];  in dcss_dtg_ch_enable()
333 	control_status |= dtg->alpha_cfg;  in dcss_dtg_ch_enable()
335 	if (dtg->control_status != control_status)  in dcss_dtg_ch_enable()
336 		dcss_dtg_write(dtg, control_status, DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_ch_enable()
338 	dtg->control_status = control_status;  in dcss_dtg_ch_enable()
341 void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en)  in dcss_dtg_vblank_irq_enable()  argument
347 		status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_vblank_irq_enable()
349 			    dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_vblank_irq_enable()
352 	dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_vblank_irq_enable()
355 void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en)  in dcss_dtg_ctxld_kick_irq_enable()  argument
361 		status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_ctxld_kick_irq_enable()
363 		if (!dtg->ctxld_kick_irq_en) {  in dcss_dtg_ctxld_kick_irq_enable()
365 				    dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_ctxld_kick_irq_enable()
366 			enable_irq(dtg->ctxld_kick_irq);  in dcss_dtg_ctxld_kick_irq_enable()
367 			dtg->ctxld_kick_irq_en = true;  in dcss_dtg_ctxld_kick_irq_enable()
369 				    dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_ctxld_kick_irq_enable()
375 	if (!dtg->ctxld_kick_irq_en)  in dcss_dtg_ctxld_kick_irq_enable()
378 	disable_irq_nosync(dtg->ctxld_kick_irq);  in dcss_dtg_ctxld_kick_irq_enable()
379 	dtg->ctxld_kick_irq_en = false;  in dcss_dtg_ctxld_kick_irq_enable()
381 	dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_ctxld_kick_irq_enable()
384 void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg)  in dcss_dtg_vblank_irq_clear()  argument
386 	dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_vblank_irq_clear()
389 bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg)  in dcss_dtg_vblank_irq_valid()  argument
391 	return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ);  in dcss_dtg_vblank_irq_valid()